From 2ee720ca45ea6dbdfe24893bba7a47248387ba2f Mon Sep 17 00:00:00 2001 From: Shelley Chen Date: Mon, 11 Feb 2019 13:06:10 -0800 Subject: mb/google/hatch: Use MEM_CH_SEL to indicate single_channel sku MEM_CH_SEL is used to indicate whether we are on a single or dual channel device, where MEM_CH_SEL = 1 for single channel skus and MEM_CH_SEL = 0 for dual channel skus. Initialize single_channel field (from GPP_F2), which will in turn initialize MemorySpdPtr pointers in cannonlake soc code. In the first build, we did not use GPP_F2, so we need to add an internal pulldown as those early devices were all dual channel devices. BUG=b:123062346, b:122959294 BRANCH=None TEST=Boot into current boards and ensure that we have 2 channels as expected Also, verify that GPP_F2 is set to 0. Change-Id: I89d022793580be603a93d0b177d73ce968529b5c Signed-off-by: Shelley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/31358 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/hatch/romstage.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/mainboard/google/hatch/romstage.c') diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage.c index 429aa09d8f..bdf951b016 100644 --- a/src/mainboard/google/hatch/romstage.c +++ b/src/mainboard/google/hatch/romstage.c @@ -23,13 +23,16 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { + struct cnl_mb_cfg memcfg; + const struct spd_info spd = { .spd_by_index = true, .spd_spec.spd_index = variant_memory_sku(), }; + variant_memory_params(&memcfg); cannonlake_memcfg_init(&memupd->FspmConfig, - variant_memory_params(), &spd); + &memcfg, &spd); } void mainboard_get_dram_part_num(const char **part_num, size_t *len) -- cgit v1.2.3