From be23f04ce7ccad902c92766b29abd1577482ec61 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Thu, 15 Feb 2024 15:36:15 -0600
Subject: soc/intel/cannonlake: select SOC_INTEL_COMMON_BLOCK_DTT

Select this at the SoC level (like other modern Intel SoCs), and drop
it from individual boards which selected it.

Change-Id: I838ada7dfe948c58a5bb9805ade289b07368aa63
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
 src/mainboard/google/hatch/Kconfig | 1 -
 1 file changed, 1 deletion(-)

(limited to 'src/mainboard/google/hatch/Kconfig')

diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index 32ce7ed045..493db33902 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -26,7 +26,6 @@ config BOARD_GOOGLE_BASEBOARD_HATCH
 	select MAINBOARD_HAS_TPM2
 	select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE
 	select SOC_INTEL_COMETLAKE_1
-	select SOC_INTEL_COMMON_BLOCK_DTT
 	select SPI_TPM
 	select SYSTEM_TYPE_LAPTOP
 	select TPM_GOOGLE_CR50
-- 
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