From 8f537442d5d1014e333ed469d0e75a87f12cfbaf Mon Sep 17 00:00:00 2001
From: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Date: Tue, 25 Dec 2018 13:21:03 +0530
Subject: mb/google/hatch: Enable console UART

This patch incorporates following changes to enable console on UART0
1. update default console number to 0
2. Enable PCI port for UART0
GPIO configuration will be done by coreboot based on correct console
number.

Change-Id: I735d33674b276b28e2cbb753d3a6d83edbabe89d
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/30424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
---
 src/mainboard/google/hatch/Kconfig | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/mainboard/google/hatch/Kconfig')

diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index 6b4e45f91b..711d2e92ba 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -45,6 +45,9 @@ config DIMM_SPD_SIZE
 config DRIVER_TPM_SPI_BUS
 	default 0x1
 
+config UART_FOR_CONSOLE
+	default 0
+
 config GBB_HWID
 	string
 	depends on CHROMEOS
-- 
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