From 0dfda74408097be2c04f9999011b8fa3f43fc7cf Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Mon, 17 Dec 2018 20:35:36 +0530 Subject: mb/google/hatch: Add SoC and EC asl files in DSDT This implementation adds below code: 1. Add SOC ACPI code in dsdt.asl -> platform.asl -> globalnvs.asl -> cpu.asl -> northbridge.asl -> southbridge.asl -> sleepstate.asl 2. Add chromeos.asl in dsdt.asl 3. Add EC ACPI code in dsdt.asl -> superio.asl -> ec.asl 4. Remove config for WAK/PTS ACPI method as chromeec doesn't implement those. BUG=b:120914069 TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot Change-Id: Icf1b1d7e34a7e863139c3583903f3b1e2cdc8da6 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/30282 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Subrata Banik --- src/mainboard/google/hatch/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'src/mainboard/google/hatch/Kconfig') diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index ef060f5c3a..b6dec1381e 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -12,7 +12,6 @@ config BOARD_GOOGLE_BASEBOARD_HATCH select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 select SOC_INTEL_CANNONLAKE_MEMCFG_INIT - select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK select SOC_INTEL_COFFEELAKE select SYSTEM_TYPE_LAPTOP -- cgit v1.2.3