From f8e440cadf4f332c676fddafd0357ecc07de5a4c Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 24 Mar 2021 00:17:35 +0100 Subject: mb/amd,google: use PAD_NF_SCI for GPIO_2 config in soc/amd based boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When GPIO_2 was configured as PAD_NF with the WAKE_L function selected the GPIO_2 override in soc_gpio_hook called soc_route_sci that wrote the corresponding SCI mapping register, but didn't set up the SCI level and trigger type, so that couldn't have worked on most of the boards. The only boards where I think this was actually tested are the google/zork ones and they configured GPIO_2 as PAD_SCI where the GPIO mux setting is GPIO mode instead of the WAKE_L mode, but at least the SCI was configured correctly. The new PAD_NF_SCI macro can configure both the right GPIO mux setting and set up the SCI configuration correctly, so use this new macro for the GPIO_2 pin. For test purposes I also added the corresponding GPIO_2 configuration to amd/mandolin to see if the affected registers end up having the expected value using the HDT debugger to look at the registers, but didn't test the wake-up functionality, since S3 resume isn't working on amd/mandolin yet. Signed-off-by: Felix Held Suggested-by: Kyösti Mälkki Change-Id: Ic069e46b759fb6746645faccd254263c49a892d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51756 Reviewed-by: Martin Roth Reviewed-by: Marshall Dawson Tested-by: build bot (Jenkins) --- src/mainboard/google/guybrush/variants/baseboard/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/google/guybrush') diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index 4f04c08d98..c43548c972 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -12,7 +12,7 @@ static const struct soc_amd_gpio base_gpio_table[] = { /* SYS_RESET_L */ PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), /* WAKE_L */ - PAD_NF(GPIO_2, WAKE_L, PULL_NONE), + PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_LOW), /* GSC_SOC_INT_L */ PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), /* SOC_PEN_DETECT_ODL */ -- cgit v1.2.3