From a7696adbeb1f3ad7408a02ba82930c02079b01ed Mon Sep 17 00:00:00 2001
From: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Date: Tue, 13 Apr 2021 14:04:12 +0800
Subject: soc/amd/cezanne: Add uart controllers to chipset.cb

Add uart controller to chipset.cb and leave it off by default.
Turn uart0 on for console for mainboards.

BUG=none
TEST=builds and boot into OS

Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: Iaeb7fea4b92bd89331c7ae7c1c000f8d9961fe9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
---
 src/mainboard/google/guybrush/variants/baseboard/devicetree.cb | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/mainboard/google/guybrush')

diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
index 5e9037abe6..f044b8be7f 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
@@ -142,4 +142,7 @@ chip soc/amd/cezanne
 			device i2c 50 on end
 		end
 	end
+
+	device ref uart_0 on end # UART0
+
 end	# chip soc/amd/cezanne
-- 
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