From 72cc0467d7ca1036787011027fc4848772b3bca0 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Tue, 19 Oct 2021 15:38:36 -0600 Subject: mb/google/guybrush: Add PCIe Reset GPIO18 to PCIE WWAN DXIO Descriptor WWAN_AUX_RST_L is asserted during S0i3 entry. But it needs to be de-asserted before PCIe link training during S0i3 resume. Otherwise the concerned gpp_bridge_2 PCIe device is not enumerated on Soi3 resume. This change feeds in the WWAN_AUX_RST_L GPIO in the DXIO descriptor so that SMU de-asserts this reset on S0i3 resume. BUG=b:199780346 TEST=Build and boot to OS in Guybrush. Perform suspend/resume cycles for 500 iterations. Ensure that the PCIe devices enumerate fine. Signed-off-by: Karthikeyan Ramasubramanian Change-Id: I588c490bf3f8a7beffefc3bfd8ca5167fcbcb9a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58459 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Marshall Dawson --- src/mainboard/google/guybrush/port_descriptors.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mainboard/google/guybrush') diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c index 177b538e64..abb854e44c 100644 --- a/src/mainboard/google/guybrush/port_descriptors.c +++ b/src/mainboard/google/guybrush/port_descriptors.c @@ -135,6 +135,9 @@ void mainboard_get_dxio_ddi_descriptors( if (is_dev_enabled(DEV_PTR(gpp_bridge_2))) guybrush_czn_dxio_descriptors[WWAN_NVME].engine_type = PCIE_ENGINE; + if (variant_has_pcie_wwan()) + guybrush_czn_dxio_descriptors[WWAN_NVME].gpio_group_id = GPIO_18; + *dxio_descs = guybrush_czn_dxio_descriptors; *dxio_num = ARRAY_SIZE(guybrush_czn_dxio_descriptors); -- cgit v1.2.3