From f33f857fbe8e190c2972d4c466a3b7f96e03cd82 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Wed, 5 May 2021 13:41:24 -0600 Subject: mb/google/guybrush: Switch eSPI ALERT# to in-band Using the push-pull alert was causing leakages when in S0i3. This is because the EC drives ALERT#, so when the AP enters S0i3, the extra current leaks into the SoC and ends up turning on the power regulators. By using in-band ALERT#, the EC no longer drives this pin high, thus fixing the leak. We could also have used an open drain alert, but the rise time is less than ideal. BUG=b:187122344, b:186135022 TEST=Measure S0i3 power on guybrush and validate it's no longer high. Signed-off-by: Raul E Rangel Change-Id: I6de771aeda8feca062652f0ea9eb57d31cb68562 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52955 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian Reviewed-by: Felix Held Reviewed-by: Furquan Shaikh Reviewed-by: Rob Barnes --- src/mainboard/google/guybrush/variants/baseboard/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/google/guybrush/variants') diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 061b27550e..88a0a1cae5 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -35,7 +35,7 @@ chip soc/amd/cezanne .io_mode = ESPI_IO_MODE_QUAD, .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, .crc_check_enable = 1, - .alert_pin = ESPI_ALERT_PIN_PUSH_PULL, + .alert_pin = ESPI_ALERT_PIN_IN_BAND, .periph_ch_en = 1, .vw_ch_en = 1, .oob_ch_en = 0, -- cgit v1.2.3