From 73674a72bcda5cde46ec1b100b1df3dc75c0908b Mon Sep 17 00:00:00 2001 From: Zheng Bao Date: Mon, 6 Dec 2021 23:10:37 +0800 Subject: mb/google/guybrush/var/nipperkin: Add Board values for eDP tuning Reference test document, update tuning registers from pass experiment setting of phy_settings. The document about eDP tuning can be gotten from the issue tracker of this ticket, at the issue tracker b/203061533#comment6. BUG=b:203061533 Change-Id: I7aa8c594d9f5caa6b2523dac079aef89e623c56f Signed-off-by: Zheng Bao Reviewed-on: https://review.coreboot.org/c/coreboot/+/59919 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Huang Reviewed-by: Jason Glenesk Reviewed-by: Raul Rangel --- .../google/guybrush/variants/nipperkin/overridetree.cb | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'src/mainboard/google/guybrush/variants') diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb index f9092a2a92..a22f36d6bd 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb @@ -225,6 +225,19 @@ chip soc/amd/cezanne .early_init = true, }" + register "edp_phy_override" = "1" + + # bit vector of phy, bit0=1: DP0, bit1=1: DP1, bit2=1: DP2, bit3=1: DP3 + register "edp_physel" = "0x1" + + register "edp_tuningset" = "{ + .dp_vs_pemph_level = 0x00, + .tx_eq_main = 0x1f, + .tx_eq_pre = 0x0, + .tx_eq_post = 0x0, + .tx_vboost_lvl = 0x5, + }" + device ref i2c_0 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" -- cgit v1.2.3