From 9a56ff9c2d2657f1cf5c9c18e96caaddd7897f68 Mon Sep 17 00:00:00 2001 From: Rob Barnes Date: Wed, 27 Oct 2021 11:25:43 -0600 Subject: mb/google/guybrush: Move EN_PWR_FP from GPIO_32 to GPIO_3 EN_PWR_FP is used to enable power to the FPMCU. This frees up GPIO_32 for other uses. This move applies to all board except: * Guybrush * Nipperkin board version 1 Add callbacks for variants to override fpmcu shtudown gpio table and fpmcu disable gpio table. BUG=b:202992077 TEST=Build and boot to OS in Guybrush and Nipperkin. Ensure fingerprint still works. Change-Id: I4501554da0fab0cb35684735e7d1da6f20e255eb Signed-off-by: Rob Barnes Reviewed-on: https://review.coreboot.org/c/coreboot/+/58660 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian Reviewed-by: Raul Rangel Reviewed-by: Marshall Dawson --- .../guybrush/variants/nipperkin/Makefile.inc | 2 + .../google/guybrush/variants/nipperkin/gpio.c | 60 ++++++++++++++++++++++ 2 files changed, 62 insertions(+) (limited to 'src/mainboard/google/guybrush/variants/nipperkin') diff --git a/src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc b/src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc index d6cd2623a2..d7ec6dd5a2 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc @@ -12,3 +12,5 @@ ramstage-y += variant.c ramstage-y += ramstage.c subdirs-y += ./memory + +smm-y += gpio.c diff --git a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c index 9a098dbb66..6a12ad3a70 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c +++ b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c @@ -22,6 +22,8 @@ static const struct soc_amd_gpio bid1_override_gpio_table[] = { PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), /* Unused */ PAD_NC(GPIO_85), + /* EN_PWR_FP */ + PAD_GPO(GPIO_32, HIGH), }; /* This table is used by nipperkin variant with board version >= 2. */ @@ -58,6 +60,38 @@ static const struct soc_amd_gpio bid2_override_pcie_gpio_table[] = { PAD_NC(GPIO_69), }; +/* This table is used by nipperkin variant with board version < 2. */ +static const struct soc_amd_gpio bid1_fpmcu_shutdown_gpio_table[] = { + /* FPMCU_RST_L */ + PAD_GPO(GPIO_11, LOW), + /* EN_PWR_FP */ + PAD_GPO(GPIO_32, LOW), +}; + +/* This table is used by nipperkin variant with board version >= 2. */ +static const struct soc_amd_gpio bid2_fpmcu_shutdown_gpio_table[] = { + /* FPMCU_RST_L */ + PAD_GPO(GPIO_11, LOW), + /* EN_PWR_FP */ + PAD_GPO(GPIO_3, LOW), +}; + +/* This table is used by nipperkin variant with board version < 2. */ +static const struct soc_amd_gpio bid1_fpmcu_disable_gpio_table[] = { + /* FPMCU_RST_L */ + PAD_NC(GPIO_11), + /* EN_PWR_FP */ + PAD_NC(GPIO_32), +}; + +/* This table is used by nipperkin variant with board version >= 2. */ +static const struct soc_amd_gpio bid2_fpmcu_disable_gpio_table[] = { + /* FPMCU_RST_L */ + PAD_NC(GPIO_11), + /* EN_PWR_FP */ + PAD_NC(GPIO_3), +}; + const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) { uint32_t board_version = board_id(); @@ -89,3 +123,29 @@ const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size) *size = ARRAY_SIZE(bid2_override_pcie_gpio_table); return bid2_override_pcie_gpio_table; } + +const struct soc_amd_gpio *variant_fpmcu_shutdown_gpio_table(size_t *size) +{ + uint32_t board_version = board_id(); + + if (board_version < 2) { + *size = ARRAY_SIZE(bid1_fpmcu_shutdown_gpio_table); + return bid1_fpmcu_shutdown_gpio_table; + } + + *size = ARRAY_SIZE(bid2_fpmcu_shutdown_gpio_table); + return bid2_fpmcu_shutdown_gpio_table; +} + +const struct soc_amd_gpio *variant_fpmcu_disable_gpio_table(size_t *size) +{ + uint32_t board_version = board_id(); + + if (board_version < 2) { + *size = ARRAY_SIZE(bid1_fpmcu_disable_gpio_table); + return bid1_fpmcu_disable_gpio_table; + } + + *size = ARRAY_SIZE(bid2_fpmcu_disable_gpio_table); + return bid2_fpmcu_disable_gpio_table; +} -- cgit v1.2.3