From a6dbfb5808b66197ea2c9b0c5e208cbd60099a12 Mon Sep 17 00:00:00 2001 From: huang lin Date: Wed, 2 Mar 2016 18:38:40 +0800 Subject: google/gru: Add a stub rk3399 mainboard Most things still need to be filled in, but this will allow us to build boards which use this SOC. [pg: separated out from the combined commit that added both SoC and board. Added board_info.txt that will be added downstream, too.] Change-Id: I7facce7b98a5d19fb77746b1aee67fff74da8150 Signed-off-by: Patrick Georgi Original-Commit-Id: 27dfc39efe95025be2271e2e00e9df93b7907840 Original-Change-Id: I6f2407ff578dcd3d0daed86dd03d8f5f4edcac53 Original-Signed-off-by: huang lin Original-Signed-off-by: Vadim Bendebury Original-Reviewed-on: https://chromium-review.googlesource.com/332385 Reviewed-on: https://review.coreboot.org/14279 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth Reviewed-by: Stefan Reinauer --- src/mainboard/google/gru/Kconfig | 67 +++++++++++++++++++++++++++++++++ src/mainboard/google/gru/Kconfig.name | 3 ++ src/mainboard/google/gru/Makefile.inc | 38 +++++++++++++++++++ src/mainboard/google/gru/board_info.txt | 6 +++ src/mainboard/google/gru/boardid.c | 28 ++++++++++++++ src/mainboard/google/gru/bootblock.c | 25 ++++++++++++ src/mainboard/google/gru/chromeos.c | 41 ++++++++++++++++++++ src/mainboard/google/gru/chromeos.fmd | 29 ++++++++++++++ src/mainboard/google/gru/devicetree.cb | 18 +++++++++ src/mainboard/google/gru/mainboard.c | 36 ++++++++++++++++++ src/mainboard/google/gru/memlayout.ld | 1 + src/mainboard/google/gru/reset.c | 21 +++++++++++ src/mainboard/google/gru/romstage.c | 34 +++++++++++++++++ 13 files changed, 347 insertions(+) create mode 100644 src/mainboard/google/gru/Kconfig create mode 100644 src/mainboard/google/gru/Kconfig.name create mode 100644 src/mainboard/google/gru/Makefile.inc create mode 100644 src/mainboard/google/gru/board_info.txt create mode 100644 src/mainboard/google/gru/boardid.c create mode 100644 src/mainboard/google/gru/bootblock.c create mode 100644 src/mainboard/google/gru/chromeos.c create mode 100644 src/mainboard/google/gru/chromeos.fmd create mode 100644 src/mainboard/google/gru/devicetree.cb create mode 100644 src/mainboard/google/gru/mainboard.c create mode 100644 src/mainboard/google/gru/memlayout.ld create mode 100644 src/mainboard/google/gru/reset.c create mode 100644 src/mainboard/google/gru/romstage.c (limited to 'src/mainboard/google/gru') diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig new file mode 100644 index 0000000000..c225d101e1 --- /dev/null +++ b/src/mainboard/google/gru/Kconfig @@ -0,0 +1,67 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2016 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config BOARD_GOOGLE_GRU # Umbrella option to be selected by variant boards. + def_bool n + +if BOARD_GOOGLE_GRU + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ID_AUTO + select BOARD_ROMSIZE_KB_8192 + select COMMON_CBFS_SPI_WRAPPER + select HAVE_HARD_RESET + select MAINBOARD_HAS_CHROMEOS + select SOC_ROCKCHIP_RK3399 + select SPI_FLASH + select SPI_FLASH_GIGADEVICE + select SPI_FLASH_WINBOND + +config CHROMEOS + select CHROMEOS_VBNV_FLASH + select VBOOT2_MOCK_SECDATA + select VIRTUAL_DEV_SWITCH + +config MAINBOARD_DIR + string + default google/gru + +config MAINBOARD_PART_NUMBER + string + default "Gru" + +config MAINBOARD_VENDOR + string + default "Google" + +config DRAM_SIZE_MB + int + default 2048 + +config EC_GOOGLE_CHROMEEC_SPI_BUS + hex + default 0 + +config BOOT_MEDIA_SPI_BUS + int + default 1 + +config CONSOLE_SERIAL_UART_ADDRESS + hex + depends on DRIVERS_UART + default 0xFF1A0000 + +endif # BOARD_GOOGLE_GRU diff --git a/src/mainboard/google/gru/Kconfig.name b/src/mainboard/google/gru/Kconfig.name new file mode 100644 index 0000000000..bd5037e87c --- /dev/null +++ b/src/mainboard/google/gru/Kconfig.name @@ -0,0 +1,3 @@ +config BOARD_GOOGLE_KEVIN + bool "Kevin" + select BOARD_GOOGLE_GRU diff --git a/src/mainboard/google/gru/Makefile.inc b/src/mainboard/google/gru/Makefile.inc new file mode 100644 index 0000000000..752830c4cc --- /dev/null +++ b/src/mainboard/google/gru/Makefile.inc @@ -0,0 +1,38 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2016 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += boardid.c +bootblock-y += bootblock.c +bootblock-y += chromeos.c +bootblock-y += memlayout.ld +bootblock-y += reset.c + +verstage-y += boardid.c +verstage-y += chromeos.c +verstage-y += memlayout.ld +verstage-y += memlayout.ld +verstage-y += reset.c + +romstage-y += boardid.c +romstage-y += chromeos.c +romstage-y += memlayout.ld +romstage-y += reset.c +romstage-y += romstage.c + +ramstage-y += boardid.c +ramstage-y += chromeos.c +ramstage-y += mainboard.c +ramstage-y += memlayout.ld +ramstage-y += reset.c diff --git a/src/mainboard/google/gru/board_info.txt b/src/mainboard/google/gru/board_info.txt new file mode 100644 index 0000000000..ced38a34b0 --- /dev/null +++ b/src/mainboard/google/gru/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Gru Rockchip RK3399 reference board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/gru/boardid.c b/src/mainboard/google/gru/boardid.c new file mode 100644 index 0000000000..f62fe97226 --- /dev/null +++ b/src/mainboard/google/gru/boardid.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +uint8_t board_id(void) +{ + return 0; +} + +uint32_t ram_code(void) +{ + return 0; +} diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c new file mode 100644 index 0000000000..bdc75dd589 --- /dev/null +++ b/src/mainboard/google/gru/bootblock.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include + +void bootblock_mainboard_early_init(void) +{ +} + +void bootblock_mainboard_init(void) +{ +} diff --git a/src/mainboard/google/gru/chromeos.c b/src/mainboard/google/gru/chromeos.c new file mode 100644 index 0000000000..6f9380d33c --- /dev/null +++ b/src/mainboard/google/gru/chromeos.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include + +void fill_lb_gpios(struct lb_gpios *gpios) +{ +} + +int get_developer_mode_switch(void) +{ + return 0; +} + +int get_recovery_mode_switch(void) +{ + return 0; +} + +int get_write_protect_state(void) +{ + return 0; +} diff --git a/src/mainboard/google/gru/chromeos.fmd b/src/mainboard/google/gru/chromeos.fmd new file mode 100644 index 0000000000..c3811707a8 --- /dev/null +++ b/src/mainboard/google/gru/chromeos.fmd @@ -0,0 +1,29 @@ +FLASH@0x0 0x800000 { + WP_RO@0x0 0x400000 { + RO_SECTION@0x0 0x3e0000 { + BOOTBLOCK@0 128K + COREBOOT(CBFS)@0x20000 0x2e0000 + FMAP@0x300000 0x1000 + GBB@0x301000 0xdef00 + RO_FRID@0x3dff00 0x100 + } + RO_VPD@0x3e0000 0x20000 + } + RW_SECTION_A@0x400000 0xe8000 { + VBLOCK_A@0x0 0x2000 + FW_MAIN_A(CBFS)@0x2000 0xe5f00 + RW_FWID_A@0xe7f00 0x100 + } + RW_VPD@0x4e8000 0x8000 + RW_SECTION_B@0x4f0000 0xe8000 { + VBLOCK_B@0x0 0x2000 + FW_MAIN_B(CBFS)@0x2000 0xe5f00 + RW_FWID_B@0xe7f00 0x100 + } + RW_ELOG@0x5d8000 0x8000 + RW_SHARED@0x5e0000 0x10000 { + SHARED_DATA@0x0 0x10000 + } + RW_NVRAM@0x5f0000 0x10000 + RW_LEGACY@0x600000 0x200000 +} diff --git a/src/mainboard/google/gru/devicetree.cb b/src/mainboard/google/gru/devicetree.cb new file mode 100644 index 0000000000..b349888302 --- /dev/null +++ b/src/mainboard/google/gru/devicetree.cb @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2016 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/rockchip/rk3399 + device cpu_cluster 0 on end +end diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c new file mode 100644 index 0000000000..1641838a5a --- /dev/null +++ b/src/mainboard/google/gru/mainboard.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include + +static void mainboard_init(device_t dev) +{ +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = CONFIG_MAINBOARD_PART_NUMBER, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/gru/memlayout.ld b/src/mainboard/google/gru/memlayout.ld new file mode 100644 index 0000000000..ead7f47838 --- /dev/null +++ b/src/mainboard/google/gru/memlayout.ld @@ -0,0 +1 @@ +#include diff --git a/src/mainboard/google/gru/reset.c b/src/mainboard/google/gru/reset.c new file mode 100644 index 0000000000..31d8b3de2d --- /dev/null +++ b/src/mainboard/google/gru/reset.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +void hard_reset(void) +{ +} diff --git a/src/mainboard/google/gru/romstage.c b/src/mainboard/google/gru/romstage.c new file mode 100644 index 0000000000..4786937acc --- /dev/null +++ b/src/mainboard/google/gru/romstage.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void main(void) +{ + console_init(); + exception_init(); + cbmem_initialize_empty(); + run_ramstage(); +} -- cgit v1.2.3