From 9e6b0ee2c4dc9130091eff45989b4585c4a2bf83 Mon Sep 17 00:00:00 2001 From: Vadim Bendebury Date: Fri, 8 Apr 2016 20:18:17 -0700 Subject: gru: kevin: initialize cr50 SPI interface Set up the pins and initialize the driver. BRANCH=none BUG=chrome-os-partner:50645, chrome-os-partner:51537 TEST=with the rest of the patches applied it is possible to communicate with the cr50. Change-Id: I9fc1cb84ccababa6f58b2d5beec4572dc1d79da1 Signed-off-by: Martin Roth Original-Commit-Id: 6100471db2a00fd411afc05d621429b8f8a2f81d Original-Change-Id: I0ccd8777288e35870658268813c9202dd850c70d Original-Signed-off-by: Vadim Bendebury Original-Reviewed-on: https://chromium-review.googlesource.com/349852 Original-Reviewed-by: Douglas Anderson Reviewed-on: https://review.coreboot.org/15296 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/gru/bootblock.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'src/mainboard/google/gru') diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c index 19e2cdebbb..0e485cf821 100644 --- a/src/mainboard/google/gru/bootblock.c +++ b/src/mainboard/google/gru/bootblock.c @@ -64,9 +64,13 @@ void bootblock_mainboard_init(void) write32(&rk3399_pmugrf->spi1_csclktx, IOMUX_SPI1_CSCLKTX); rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); - /* Set pinmux and configure EC flashrom. */ + /* Set pinmux and configure EC SPI. */ write32(&rk3399_grf->iomux_spi5, IOMUX_SPI5); rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 3093750); + /* Set pinmux and configure TPM SPI, which is not very fast. */ + write32(&rk3399_grf->iomux_spi0, IOMUX_SPI0); + rockchip_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, 1500*KHz); + setup_chromeos_gpios(); } -- cgit v1.2.3