From f08f38883ea1a5c12bd1ece1736e336c20645e7c Mon Sep 17 00:00:00 2001 From: Lin Huang Date: Wed, 21 Sep 2016 17:05:43 +0800 Subject: google/gru: set W2W_DIFFCS_DLY to 5 PHY_PER_CS_TRAINING is being enabled when DDR frequency >= 666. For per cs training, the controller should consider the PHY delay line switch time and there should be more cycles to switch the delay line, so update the W2W_DIFFCS_DLY_ value from 0x1 to 0x5. BRANCH=none BUG=chrome-os-partner:56940 TEST=do memtester on kevin board, and pass Change-Id: I00df2d4724b0b77f3e7565809fb35bbd2ff01ea5 Signed-off-by: Patrick Georgi Original-Commit-Id: c135ea3e33d810ed322d947eb8d512d1ac119cfc Original-Change-Id: I81b99cbc085769b7028e770509d79bd8d550820b Original-Signed-off-by: Lin Huang Original-Reviewed-on: https://chromium-review.googlesource.com/387506 Original-Reviewed-by: Douglas Anderson Original-Reviewed-by: Derek Basehore Original-Reviewed-by: Julius Werner Reviewed-on: https://review.coreboot.org/16721 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c') diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c index b7386445af..3056e55b20 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c @@ -279,8 +279,8 @@ struct rk3399_sdram_params params = { 0x0a0a0a03, /* DENALI_CTL_215_DATA */ 0x08080808, /* DENALI_CTL_216_DATA */ 0x02050103, /* DENALI_CTL_217_DATA */ - 0x02010103, /* DENALI_CTL_218_DATA */ - 0x00010103, /* DENALI_CTL_219_DATA */ + 0x02050103, /* DENALI_CTL_218_DATA */ + 0x00050103, /* DENALI_CTL_219_DATA */ 0x00020202, /* DENALI_CTL_220_DATA */ 0x03020500, /* DENALI_CTL_221_DATA */ 0x00020501, /* DENALI_CTL_222_DATA */ -- cgit v1.2.3