From 6c83a71b0a803c922b02b613e927d4c49b944c32 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Sun, 23 Jun 2024 00:25:18 +0200 Subject: skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scope MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/83171 Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai Reviewed-by: Marvin Evers Reviewed-by: Erik van den Bogaert Reviewed-by: Michael Niewöhner Reviewed-by: Jonathon Hall --- .../google/glados/variants/lars/overridetree.cb | 29 +++++++++++++--------- 1 file changed, 17 insertions(+), 12 deletions(-) (limited to 'src/mainboard/google/glados/variants/lars/overridetree.cb') diff --git a/src/mainboard/google/glados/variants/lars/overridetree.cb b/src/mainboard/google/glados/variants/lars/overridetree.cb index 2616044e51..1165520208 100644 --- a/src/mainboard/google/glados/variants/lars/overridetree.cb +++ b/src/mainboard/google/glados/variants/lars/overridetree.cb @@ -1,18 +1,23 @@ chip soc/intel/skylake - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-C Port 1 - register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # Type-A Port (card) - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # SD - register "usb2_ports[8]" = "USB2_PORT_LONG(OC3)" # Type-A Port (board) - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (card) - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board) - device domain 0 on + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_TYPE_C(OC0), // Type-C Port 1 + [1] = USB2_PORT_FLEX(OC_SKIP), // Camera + [2] = USB2_PORT_MID(OC_SKIP), // Bluetooth + [4] = USB2_PORT_MID(OC2), // Type-A Port (card) + [5] = USB2_PORT_MID(OC_SKIP), // SD + [8] = USB2_PORT_LONG(OC3), // Type-A Port (board) + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), // Type-C Port 1 + [1] = USB3_PORT_DEFAULT(OC_SKIP), // SD + [2] = USB3_PORT_DEFAULT(OC2), // Type-A Port (card) + [3] = USB3_PORT_DEFAULT(OC3), // Type-A Port (board) + }" + end device ref i2c0 on chip drivers/i2c/generic register "hid" = ""ELAN0001"" -- cgit v1.2.3