From d9e568a0464796b0d5e6209f4c5e3d7ed42e59b2 Mon Sep 17 00:00:00 2001
From: Rex-BC Chen <rex-bc.chen@mediatek.com>
Date: Mon, 25 Jul 2022 19:36:56 +0800
Subject: mb/google/geralt: Configure TPM

Initialize I2C bus 1 for TPM control.

TEST=build pass
BUG=b:236331724

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: If5807c9bb39260315ecbc55305def483bd2b8c51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66273
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/geralt/Kconfig     | 11 +++++++++++
 src/mainboard/google/geralt/bootblock.c |  6 ++++++
 src/mainboard/google/geralt/chromeos.c  |  9 +++++++++
 src/mainboard/google/geralt/gpio.h      |  1 +
 4 files changed, 27 insertions(+)

(limited to 'src/mainboard/google/geralt')

diff --git a/src/mainboard/google/geralt/Kconfig b/src/mainboard/google/geralt/Kconfig
index 0501a1d34f..9655bca100 100644
--- a/src/mainboard/google/geralt/Kconfig
+++ b/src/mainboard/google/geralt/Kconfig
@@ -24,6 +24,9 @@ config BOARD_SPECIFIC_OPTIONS
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_BOARDID
 	select EC_GOOGLE_CHROMEEC_SPI
+	select I2C_TPM if VBOOT
+	select MAINBOARD_HAS_TPM2 if VBOOT
+	select TPM_GOOGLE_TI50 if VBOOT
 
 config MAINBOARD_DIR
 	string
@@ -40,4 +43,12 @@ config BOOT_DEVICE_SPI_FLASH_BUS
 config EC_GOOGLE_CHROMEEC_SPI_BUS
 	hex
 	default 0x0
+
+config DRIVER_TPM_I2C_BUS
+	hex
+	default 0x1
+
+config DRIVER_TPM_I2C_ADDR
+	hex
+	default 0x50
 endif
diff --git a/src/mainboard/google/geralt/bootblock.c b/src/mainboard/google/geralt/bootblock.c
index ef7e5d1fbf..9a76b368ca 100644
--- a/src/mainboard/google/geralt/bootblock.c
+++ b/src/mainboard/google/geralt/bootblock.c
@@ -2,10 +2,16 @@
 
 #include <bootblock_common.h>
 #include <device/mmio.h>
+#include <soc/gpio.h>
+#include <soc/i2c.h>
 #include <soc/spi.h>
 
+#include "gpio.h"
+
 void bootblock_mainboard_init(void)
 {
+	mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST);
 	mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0);
 	mtk_snfc_init();
+	gpio_eint_configure(GPIO_GSC_AP_INT_ODL, IRQ_TYPE_EDGE_RISING);
 }
diff --git a/src/mainboard/google/geralt/chromeos.c b/src/mainboard/google/geralt/chromeos.c
index 434ff90659..eb93be20c4 100644
--- a/src/mainboard/google/geralt/chromeos.c
+++ b/src/mainboard/google/geralt/chromeos.c
@@ -2,8 +2,17 @@
 
 #include <bootmode.h>
 #include <boot/coreboot_tables.h>
+#include <gpio.h>
+#include <security/tpm/tis.h>
+
+#include "gpio.h"
 
 void fill_lb_gpios(struct lb_gpios *gpios)
 {
 	/* TODO: add Chrome specific gpios */
 }
+
+int tis_plat_irq_status(void)
+{
+	return gpio_eint_poll(GPIO_GSC_AP_INT_ODL);
+}
diff --git a/src/mainboard/google/geralt/gpio.h b/src/mainboard/google/geralt/gpio.h
index 386df4d1b3..ff6de17563 100644
--- a/src/mainboard/google/geralt/gpio.h
+++ b/src/mainboard/google/geralt/gpio.h
@@ -6,6 +6,7 @@
 #include <soc/gpio.h>
 
 #define GPIO_AP_EC_WARM_RST_REQ	GPIO(DPI_HSYNC)
+#define GPIO_GSC_AP_INT_ODL	GPIO(GPIO00)
 
 void setup_chromeos_gpios(void);
 
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