From 125082091655feb99892f1af440f282213f3037f Mon Sep 17 00:00:00 2001
From: Rex-BC Chen <rex-bc.chen@mediatek.com>
Date: Mon, 25 Jul 2022 19:08:06 +0800
Subject: mb/google/geralt: Enable Chrome EC

Initialize SPI bus 0 for Chrome EC control.

TEST=build pass
BUG=b:236331724

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I6de5ea8a0273a3b0c725e4cdbcf69f4db74c5db7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/mainboard/google/geralt/reset.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

(limited to 'src/mainboard/google/geralt/reset.c')

diff --git a/src/mainboard/google/geralt/reset.c b/src/mainboard/google/geralt/reset.c
index 3eb13907b8..05a576b69c 100644
--- a/src/mainboard/google/geralt/reset.c
+++ b/src/mainboard/google/geralt/reset.c
@@ -1,8 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <gpio.h>
 #include <reset.h>
 
+#include "gpio.h"
+
 void do_board_reset(void)
 {
-	/* TODO: add reset function when gpio is ready */
+	gpio_output(GPIO_AP_EC_WARM_RST_REQ, 1);
 }
-- 
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