From 10c37492076fdfcdb778bd1e5ddf327cf5f814f5 Mon Sep 17 00:00:00 2001 From: Varadarajan Narayanan Date: Thu, 17 Mar 2016 14:37:56 +0530 Subject: soc/qualcomm/ipq40xx: Update memory map to align to ipq40xx Update the memory to map to align with the internal memory region map of IPQ40XX BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Original-Commit-Id: e33712a729ef9831508c2e9aae81d0b32495b681 Original-Change-Id: Iba1c5281a2fbda4ab96126676b901ba71f6b28e0 Original-Signed-off-by: Varadarajan Narayanan Original-Reviewed-on: https://chromium-review.googlesource.com/333295 Original-Reviewed-by: David Hendricks squashed: soc/qualcomm/ipq40xx: Update DRAM address ranges BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Original-Commit-Id: 9150c125cb82f8dccb1347d898106703d85a5192 Original-Change-Id: Ic48d3e3f46a7c13a009a5cbed20984bd253eb85b Original-Signed-off-by: Varadarajan Narayanan Original-Reviewed-on: https://chromium-review.googlesource.com/333296 Original-Reviewed-by: David Hendricks Change-Id: Iea40484751a1c0439ed511319ef09a0254eba757 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/14654 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/mainboard/google/gale/mmu.c | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) (limited to 'src/mainboard/google/gale/mmu.c') diff --git a/src/mainboard/google/gale/mmu.c b/src/mainboard/google/gale/mmu.c index 4d2e9a0123..65797e7463 100644 --- a/src/mainboard/google/gale/mmu.c +++ b/src/mainboard/google/gale/mmu.c @@ -14,15 +14,14 @@ #include #include "mmu.h" -/* convenient shorthand (in MB) */ -#define RPM_START ((uintptr_t)_rpm / KiB) -#define RPM_END ((uintptr_t)_erpm / KiB) -#define RPM_SIZE (RPM_END - RPM_START) -#define SRAM_START ((uintptr_t)_sram / KiB) -#define SRAM_END ((uintptr_t)_esram / KiB) -#define DRAM_START ((uintptr_t)_dram / MiB) -#define DRAM_SIZE (CONFIG_DRAM_SIZE_MB) -#define DRAM_END (DRAM_START + DRAM_SIZE) +#define WIFI_IMEM_0_START ((uintptr_t)_wifi_imem_0 / KiB) +#define WIFI_IMEM_0_END ((uintptr_t)_ewifi_imem_0 / KiB) +#define WIFI_IMEM_1_START ((uintptr_t)_wifi_imem_1 / KiB) +#define WIFI_IMEM_1_END ((uintptr_t)_ewifi_imem_1 / KiB) + +#define DRAM_START ((uintptr_t)_dram / MiB) +#define DRAM_SIZE (CONFIG_DRAM_SIZE_MB) +#define DRAM_END (DRAM_START + DRAM_SIZE) /* DMA memory for drivers */ #define DMA_START ((uintptr_t)_dma_coherent / MiB) @@ -45,14 +44,19 @@ void setup_mmu(enum dram_state dram) { dcache_mmu_disable(); + mmu_init(); + /* start with mapping everything as strongly ordered. */ mmu_config_range(0, 4096, DCACHE_OFF); /* Map Device memory. */ - mmu_config_range_kb(RPM_START, RPM_SIZE, DCACHE_OFF); + mmu_config_range_kb(WIFI_IMEM_0_START, + WIFI_IMEM_0_END - WIFI_IMEM_0_START, + DCACHE_WRITEBACK); - mmu_config_range_kb(SRAM_START, SRAM_END - SRAM_START, - DCACHE_WRITEBACK); + mmu_config_range_kb(WIFI_IMEM_1_START, + WIFI_IMEM_1_END - WIFI_IMEM_1_START, + DCACHE_WRITEBACK); /* Map DRAM memory */ setup_dram_mappings(dram); @@ -62,7 +66,5 @@ void setup_mmu(enum dram_state dram) /* disable Page 0 for trapping NULL pointer references. */ mmu_disable_range_kb(0, 1); - mmu_init(); - dcache_mmu_enable(); } -- cgit v1.2.3