From c204aaa23b8455457920a56a85b0128f9818f461 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 17 Aug 2017 15:49:58 +0530 Subject: soc/intel/skylake: Add LPC and SPI lock down config option This patch to provide new config options to perform LPC and SPI lock down either by FSP or coreboot. Remove EISS bit programming as well. TEST=Build and boot Eve and Poppy. Change-Id: If174915b4d0c581f36b54b2b8cd970a93c6454bc Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/21068 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/google/fizz/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mainboard/google/fizz') diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index bf9f0c9ef9..a771380238 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -216,6 +216,9 @@ chip soc/intel/skylake # Use default SD card detect GPIO configuration register "sdcard_cd_gpio_default" = "GPP_A7" + # Lock Down + register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT" + device cpu_cluster 0 on device lapic 0 on end end -- cgit v1.2.3