From 6dd9e5983e7ba339f9a7f891251fd99eb73b4c85 Mon Sep 17 00:00:00 2001
From: Shelley Chen <shchen@chromium.org>
Date: Wed, 20 Dec 2017 10:43:25 -0800
Subject: mainboard/google/fizz: Enable S0ix

Enable S0ix for fizz.

BUG=b:67598361
BRANCH=None
TEST=None.  Need to be tested with EC and kernel as well.

Change-Id: I981d2cc7e969a44567b0f21f63f68c78e73f5cb5
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22955
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
---
 src/mainboard/google/fizz/devicetree.cb | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/mainboard/google/fizz')

diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb
index db6c83f2ed..1ee54aaa60 100644
--- a/src/mainboard/google/fizz/devicetree.cb
+++ b/src/mainboard/google/fizz/devicetree.cb
@@ -50,6 +50,9 @@ chip soc/intel/skylake
 	# Enable DPTF
 	register "dptf_enable" = "1"
 
+	# Enable S0ix
+	register "s0ix_enable" = "1"
+
 	# FSP Configuration
 	register "ProbelessTrace" = "0"
 	register "EnableLan" = "1"
-- 
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