From 3918887c1829fa0c4ccd18a95f3c26e92fad330c Mon Sep 17 00:00:00 2001 From: Shelley Chen Date: Wed, 11 Oct 2017 15:39:08 -0700 Subject: google/fizz: Enable cr50 over SPI We are changing the bootstraps in the EVTs so that the SOC communicates with cr50 over SPI instead of cr50. SPI is more reliable than I2C. Thus, disabling cr50 over I2C and enabling cr50 over SPI. BUG=b:65056998, b:62456589 BRANCH=None TEST=make sure that we can boot into kernel run cold_reset and warm_reset and make sure both boot successfully. CQ-DEPEND=CL:714237 Change-Id: I85b9a61f0305e3c7ccada79d7702234a285a6d2a Signed-off-by: Shelley Chen Reviewed-on: https://review.coreboot.org/21970 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh --- src/mainboard/google/fizz/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/google/fizz') diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index e4154bbf81..34e3881b21 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -15,7 +15,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_USES_FSP2_0 select NO_FADT_8042 select SOC_INTEL_KABYLAKE - select FIZZ_USE_I2C_TPM + select FIZZ_USE_SPI_TPM select GENERIC_SPD_BIN select RT8168_GET_MAC_FROM_VPD -- cgit v1.2.3