From 6c83a71b0a803c922b02b613e927d4c49b944c32 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Sun, 23 Jun 2024 00:25:18 +0200 Subject: skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scope MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/83171 Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai Reviewed-by: Marvin Evers Reviewed-by: Erik van den Bogaert Reviewed-by: Michael Niewöhner Reviewed-by: Jonathon Hall --- .../google/fizz/variants/endeavour/overridetree.cb | 31 ++++++++++++---------- 1 file changed, 17 insertions(+), 14 deletions(-) (limited to 'src/mainboard/google/fizz/variants/endeavour') diff --git a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb index 989b2406fb..3da4f0e4f6 100644 --- a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb +++ b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb @@ -42,20 +42,6 @@ chip soc/intel/skylake register "PcieRpEnable[10]" = "0" register "PcieRpEnable[11]" = "0" - register "usb2_ports[0]" = "USB2_PORT_LONG(OC_SKIP)" # Type-C - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # HDMI - register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Rear - register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # Type-A Rear - register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-A Rear - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # HDMI Audio - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # HDMI - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Rear - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Rear - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Rear - register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # TPU register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # TPM register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" # None @@ -78,6 +64,23 @@ chip soc/intel/skylake device domain 0 on device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_LONG(OC_SKIP), // Type-C + [1] = USB2_PORT_MID(OC_SKIP), // HDMI + [2] = USB2_PORT_MID(OC2), // Type-A Rear + [3] = USB2_PORT_MID(OC2), // Type-A Rear + [4] = USB2_PORT_MID(OC3), // Type-A Rear + [5] = USB2_PORT_MID(OC_SKIP), // HDMI Audio + [6] = USB2_PORT_MID(OC_SKIP), // Bluetooth + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), // Type-C + [1] = USB3_PORT_DEFAULT(OC_SKIP), // HDMI + [2] = USB3_PORT_DEFAULT(OC2), // Type-A Rear + [3] = USB3_PORT_DEFAULT(OC2), // Type-A Rear + [4] = USB3_PORT_DEFAULT(OC3), // Type-A Rear + }" chip drivers/usb/acpi device usb 0.0 on chip drivers/usb/acpi -- cgit v1.2.3