From 893c3ae892961facc9be8bd300160222e694ab34 Mon Sep 17 00:00:00 2001 From: Alexander Goncharov Date: Sat, 4 Feb 2023 15:20:37 +0400 Subject: tree: Drop repeated words Found-by: linter Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b Signed-off-by: Alexander Goncharov Reviewed-on: https://review.coreboot.org/c/coreboot/+/72795 Reviewed-by: Nicholas Chin Reviewed-by: Elyes Haouas Reviewed-by: Eric Lai Reviewed-by: Erik van den Bogaert Reviewed-by: Frans Hendriks Tested-by: build bot (Jenkins) --- src/mainboard/google/fizz/variants/baseboard/devicetree.cb | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src/mainboard/google/fizz/variants/baseboard/devicetree.cb') diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 95d5368f52..74c601a58f 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -168,7 +168,7 @@ chip soc/intel/skylake register "PcieRpAdvancedErrorReporting[2]" = "1" # RP 3, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[2]" = "1" - # RP 3 uses uses CLK SRC 0 + # RP 3 uses CLK SRC 0 register "PcieRpClkSrcNumber[2]" = "0" # Enable Root port 4(x1) for WLAN. @@ -181,7 +181,7 @@ chip soc/intel/skylake register "PcieRpAdvancedErrorReporting[3]" = "1" # RP 4, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[3]" = "1" - # RP 4 uses uses CLK SRC 5 + # RP 4 uses CLK SRC 5 register "PcieRpClkSrcNumber[3]" = "5" # Enable Root port 5(x4) for NVMe. @@ -207,7 +207,7 @@ chip soc/intel/skylake register "PcieRpAdvancedErrorReporting[8]" = "1" # RP 9, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[8]" = "1" - # RP 9 uses uses CLK SRC 2 + # RP 9 uses CLK SRC 2 register "PcieRpClkSrcNumber[8]" = "2" # Enable Root port 11 for BtoB. @@ -220,7 +220,7 @@ chip soc/intel/skylake register "PcieRpAdvancedErrorReporting[10]" = "1" # RP 11, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[10]" = "1" - # RP 11 uses uses CLK SRC 2 + # RP 11 uses CLK SRC 2 register "PcieRpClkSrcNumber[10]" = "2" # Enable Root port 12 for BtoB. @@ -233,7 +233,7 @@ chip soc/intel/skylake register "PcieRpAdvancedErrorReporting[11]" = "1" # RP 12, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[11]" = "1" - # RP 12 uses uses CLK SRC 2 + # RP 12 uses CLK SRC 2 register "PcieRpClkSrcNumber[11]" = "2" register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C -- cgit v1.2.3