From db287aad2547d6bc4a710c8a511448b5ff5ebead Mon Sep 17 00:00:00 2001 From: Shelley Chen Date: Fri, 9 Jun 2017 12:56:08 -0700 Subject: google/fizz: Enable cr50 over i2c BUG=b:62456589, b:35775024 BRANCH=None TEST=Reboot and ensure verstage doesn't have any TPM errors CQ-DEPEND=CL:530185 Change-Id: Icfde0f62bd058d960fcb0c6fc67f9d8f6b9462f5 Signed-off-by: Shelley Chen Reviewed-on: https://review.coreboot.org/20133 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/fizz/Kconfig | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'src/mainboard/google/fizz/Kconfig') diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index 2d2e6b78c0..da6e67465b 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -13,12 +13,21 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_USES_FSP2_0 select NO_FADT_8042 select SOC_INTEL_KABYLAKE + select FIZZ_USE_I2C_TPM select GENERIC_SPD_BIN config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC +config DRIVER_TPM_I2C_BUS + depends on FIZZ_USE_I2C_TPM + default 0x1 + +config DRIVER_TPM_I2C_ADDR + depends on FIZZ_USE_I2C_TPM + default 0x50 + config GBB_HWID string depends on CHROMEOS @@ -47,4 +56,17 @@ config DIMM_MAX config DIMM_SPD_SIZE int default 512 + +# Select this option to enable use of cr50 I2C TPM on fizz. +config FIZZ_USE_I2C_TPM + bool + default n + select I2C_TPM + select MAINBOARD_HAS_I2C_TPM_CR50 + select TPM2 + +config TPM_TIS_ACPI_INTERRUPT + int + default 64 # GPE0_DW2_00 (GPP_E0) + endif -- cgit v1.2.3