From 937cac30abac48ab8c22b85aaedcf65bb2f244b0 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 25 Oct 2024 14:05:37 +0530 Subject: mb/google/fatcat: Drop LOCK_CONFIG for GPP_D15 in early GPIO config Ideally lock configuration is not applicable for early GPIO configuration (like bootblock/romstage) and is only required for GPIO PAD configuration by later statge (like ramstage). The GPP_D15 pin was previously configured with LOCK_CONFIG in the early bootblock GPIO configuration. This is not necessary and prevents later boot stages from configuring this GPIO. Change-Id: Ie0e648b750d7579def39ed95eab862dc3245499c Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/84867 Tested-by: build bot (Jenkins) Reviewed-by: Pranava Y N Reviewed-by: Cliff Huang --- src/mainboard/google/fatcat/variants/fatcat/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/google/fatcat/variants') diff --git a/src/mainboard/google/fatcat/variants/fatcat/gpio.c b/src/mainboard/google/fatcat/variants/fatcat/gpio.c index 43362b88f9..ca594465da 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/gpio.c +++ b/src/mainboard/google/fatcat/variants/fatcat/gpio.c @@ -413,7 +413,7 @@ static const struct pad_config early_gpio_table[] = { /* GPP_H07: I2C3_SCL_PSS */ PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), /* GPP_D15: SPI_TPM_INT_N */ - PAD_CFG_GPI_APIC_LOCK(GPP_D15, NONE, LEVEL, INVERT, LOCK_CONFIG), + PAD_CFG_GPI_APIC(GPP_D15, NONE, PLTRST, LEVEL, INVERT), }; /* Pad configuration in romstage */ -- cgit v1.2.3