From e7fb7ce06577d88a193c8553b2d94c12eb256c58 Mon Sep 17 00:00:00 2001 From: Divya Chellap Date: Tue, 19 Dec 2017 20:16:50 +0530 Subject: soc/intel/skylake: Add PcieRpClkSrcNumber UPD configuartion support New UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to configure clock source number of PCIe root ports. This UPD array is set to clock source number(0-6) for all the enabled PCIe root ports, invalid(0x1F) is set for disabled PCIe root ports. BUG=b:70252901 BRANCH=None TEST= Perform the following 1. Build and boot soraka 2. Verify PCIe devices list using lspci command 3. Perform Basic Assurance Test(BAT) on soraka Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e Signed-off-by: Divya Chellap Reviewed-on: https://review.coreboot.org/22947 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Subrata Banik Reviewed-by: Furquan Shaikh --- src/mainboard/google/eve/devicetree.cb | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/mainboard/google/eve') diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index a0b0ea6194..2880066873 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -146,6 +146,8 @@ chip soc/intel/skylake register "PcieRpClkReqNumber[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" register "PcieRpLtrEnable[0]" = "1" + #RP 1 uses CLK SRC 1 + register "PcieRpClkSrcNumber[0]" = "1" # Enable Root port 5 with SRCCLKREQ4# register "PcieRpEnable[4]" = "1" @@ -153,6 +155,8 @@ chip soc/intel/skylake register "PcieRpClkReqNumber[4]" = "4" register "PcieRpAdvancedErrorReporting[4]" = "1" register "PcieRpLtrEnable[4]" = "1" + #RP 5 uses CLK SRC 4 + register "PcieRpClkSrcNumber[4]" = "4" register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera -- cgit v1.2.3