From 57dcf55538e192b65f568eb7452043634fc49fce Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Thu, 8 Dec 2016 10:48:06 -0800 Subject: google/eve: Add ASL code to describe SPI FPC1020 controller There is ongoing work to link SPI bus and devices in to the devicetree so this can be generated, but for now put in the raw ASL code to describe this controller so it can be used by the factory. BUG=chrome-os-partner:55538 TEST=successfully load fpc1020 kernel module on eve board Change-Id: I6641664e60fcf2c0bad4b3506c77513b26d7be2e Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/17776 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/google/eve/acpi/mainboard.asl | 49 +++++++++++++++++++++++++++++ src/mainboard/google/eve/dsdt.asl | 3 ++ 2 files changed, 52 insertions(+) create mode 100644 src/mainboard/google/eve/acpi/mainboard.asl (limited to 'src/mainboard/google/eve') diff --git a/src/mainboard/google/eve/acpi/mainboard.asl b/src/mainboard/google/eve/acpi/mainboard.asl new file mode 100644 index 0000000000..a55308ff31 --- /dev/null +++ b/src/mainboard/google/eve/acpi/mainboard.asl @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.SPI1) +{ + Device (FPC) + { + Name (_HID, "PRP0001") + Name (_UID, 1) + Name (_CRS, ResourceTemplate () + { + SpiSerialBus ( + 0, // DeviceSelection (CS0) + PolarityLow, // DeviceSelectionPolarity + FourWireMode, // WireMode + 8, // DataBitLength + ControllerInitiated, // SlaveMode + 1000000, // ConnectionSpeed (1MHz) + ClockPolarityLow, // ClockPolarity + ClockPhaseFirst, // ClockPhase + "\\_SB.PCI0.SPI1", // ResourceSource + 0, // ResourceSourceIndex + ResourceConsumer, // ResourceUsage + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) { 0x50 } + }) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { + "compatible", + Package () { "fpc,fpc1020" } + }, + } + }) + } +} diff --git a/src/mainboard/google/eve/dsdt.asl b/src/mainboard/google/eve/dsdt.asl index 2882d50f19..22b92f3194 100644 --- a/src/mainboard/google/eve/dsdt.asl +++ b/src/mainboard/google/eve/dsdt.asl @@ -67,4 +67,7 @@ DefinitionBlock( { #include "acpi/dptf.asl" } + + /* ACPI code for EC functions */ + #include "acpi/mainboard.asl" } -- cgit v1.2.3