From 219ebb969bb52eb88d49d6ce31dbfc0d7cabfc49 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 6 Oct 2017 17:05:50 -0700 Subject: skylake mainboards: Use PAD_CFG_GPI_GPIO_DRIVER instead of PAD_CFG_GPI Change 1760cd3e (soc/intel/skylake: Use common/block/gpio) updated all skylake boards to use common gpio driver. Common gpio code defines PAD_CFG_GPI without GPIO_DRIVER ownership. However, for skylake PAD_CFG_GPI set GPIO_DRIVER ownership by default. This resulted in Linux kernel failing to configure all GPIO IRQs since the ownership was not set correctly. (Observed error in dmesg: "genirq: Setting trigger mode 3 for irq 201 failed (intel_gpio_irq_type+0x0/0x110)") This change fixes the above issue by replacing all uses of PAD_CFG_GPI in skylake mainboards to PAD_CFG_GPI_GPIO_DRIVER. BUG=b:67507004 TEST=Verified on soraka that the genirq error is no longer observed in dmesg. Also, cat /proc/interrupts has the interrupts configured correctly. Change-Id: I7dab302f372e56864432100a56462b92d43060ee Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/21912 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/google/eve/gpio.h | 41 ++++++++++++++++++++++++++--------------- 1 file changed, 26 insertions(+), 15 deletions(-) (limited to 'src/mainboard/google/eve') diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h index b8850690ff..b9b37a07a2 100644 --- a/src/mainboard/google/eve/gpio.h +++ b/src/mainboard/google/eve/gpio.h @@ -100,16 +100,21 @@ static const struct pad_config gpio_table[] = { /* SML0CLK */ PAD_CFG_NC(GPP_C3), /* SML0DATA */ PAD_CFG_NC(GPP_C4), /* SML0ALERT# */ PAD_CFG_NC(GPP_C5), -/* SM1CLK */ PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */ +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, + DEEP), /* EC_IN_RW */ /* SM1DATA */ PAD_CFG_NC(GPP_C7), /* UART0_RXD */ PAD_CFG_NC(GPP_C8), /* UART0_TXD */ PAD_CFG_NC(GPP_C9), /* UART0_RTS# */ PAD_CFG_NC(GPP_C10), /* UART0_CTS# */ PAD_CFG_NC(GPP_C11), -/* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */ -/* UART1_TXD */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */ -/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */ -/* UART1_CTS# */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* MEM_CONFIG[3] */ +/* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, + DEEP), /* MEM_CONFIG[0] */ +/* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, + DEEP), /* MEM_CONFIG[1] */ +/* UART1_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, + DEEP), /* MEM_CONFIG[2] */ +/* UART1_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, + DEEP), /* MEM_CONFIG[3] */ /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TOUCHSCREEN */ /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TOUCHSCREEN */ /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* TPM */ @@ -117,10 +122,12 @@ static const struct pad_config gpio_table[] = { /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ /* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 0, DEEP), /* EN_PP3300_DX_TOUCHSCREEN */ -/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, + DEEP), /* PCH_WP */ /* SPI1_CS# */ PAD_CFG_GPO(GPP_D0, 0, DEEP), /* TOUCHPAD_BOOT */ -/* SPI1_CLK */ PAD_CFG_GPI(GPP_D1, NONE, DEEP), /* TOUCHPAD_RESET */ +/* SPI1_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D1, NONE, + DEEP), /* TOUCHPAD_RESET */ /* SPI1_MISO */ PAD_CFG_NC(GPP_D2), /* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), /* FASHTRIG */ PAD_CFG_NC(GPP_D4), @@ -155,7 +162,8 @@ static const struct pad_config gpio_table[] = { /* SATALED# */ PAD_CFG_NC(GPP_E8), /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_C0_OC_ODL */ /* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_C1_OC_ODL */ -/* USB2_OC2# */ PAD_CFG_GPI(GPP_E11, NONE, DEEP), /* TOUCHSCREEN_STOP_L */ +/* USB2_OC2# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E11, NONE, + DEEP), /* TOUCHSCREEN_STOP_L */ /* USB2_OC3# */ PAD_CFG_NC(GPP_E12), /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1), /* USB_C0_DP_HPD */ /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1), /* USB_C1_DP_HPD */ @@ -170,14 +178,16 @@ static const struct pad_config gpio_table[] = { /* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23), /* The next 4 pads are for bit banging the amplifiers, default to I2S */ -/* I2S2_SCLK */ PAD_CFG_GPI(GPP_F0, NONE, DEEP), -/* I2S2_SFRM */ PAD_CFG_GPI(GPP_F1, NONE, DEEP), -/* I2S2_TXD */ PAD_CFG_GPI(GPP_F2, NONE, DEEP), -/* I2S2_RXD */ PAD_CFG_GPI(GPP_F3, NONE, DEEP), +/* I2S2_SCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP), +/* I2S2_SFRM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP), +/* I2S2_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), +/* I2S2_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP), /* I2C2_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), /* TOUCHPAD */ /* I2C2_SCL */ PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), /* TOUCHPAD */ -/* I2C3_SDA */ PAD_CFG_GPI(GPP_F6, NONE, DEEP), /* DISPLAY is master */ -/* I2C3_SCL */ PAD_CFG_GPI(GPP_F7, NONE, DEEP), /* DISPLAY is master */ +/* I2C3_SDA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F6, NONE, + DEEP), /* DISPLAY is master */ +/* I2C3_SCL */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F7, NONE, + DEEP), /* DISPLAY is master */ /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* AUDIO1V8_SDA */ /* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* AUDIO1V8_SCL */ /* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ @@ -222,7 +232,8 @@ static const struct pad_config gpio_table[] = { static const struct pad_config early_gpio_table[] = { /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* TPM */ /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* TPM */ -/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, + DEEP), /* PCH_WP */ /* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* TPM_INT_L */ /* Ensure UART pins are in native mode for H1 */ -- cgit v1.2.3