From 03df460af5f73bb2fbbe23caff5f0bb646e8f756 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Tue, 7 Mar 2017 18:59:19 -0800 Subject: google/eve: Configure GPIOs for new board A new board revision is making use of two previously unused GPIOs to drive BOOT/RESET pins to an on-board MCU. The reset pin is open drain so it is set as input by default, and the boot pin is driven low by default. Since these are UART0 pins they also need to be set up again after executing FSP-S as it will change them back to native mode pins. BUG=b:36025702 BRANCH=none TEST=manual testing on reworked board, toggling GPIOs to put the MCU into programming mode. Change-Id: Id6f0ef2f863bc1e873b58e344446038786b59d25 Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/18661 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/mainboard/google/eve/gpio.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'src/mainboard/google/eve') diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h index 85011f129a..deb0192111 100644 --- a/src/mainboard/google/eve/gpio.h +++ b/src/mainboard/google/eve/gpio.h @@ -105,8 +105,8 @@ static const struct pad_config gpio_table[] = { /* SM1DATA */ PAD_CFG_NC(GPP_C7), /* UART0_RXD */ PAD_CFG_GPI(GPP_C8, NONE, PLTRST), /* FP_INT */ /* UART0_TXD */ PAD_CFG_GPO(GPP_C9, 1, DEEP), /* FP_RST_ODL */ -/* UART0_RTS# */ PAD_CFG_NC(GPP_C10), -/* UART0_CTS# */ PAD_CFG_NC(GPP_C11), +/* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* PCH_FPS_MCU_NRST_ODL */ +/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FPS_MCU_BOOT0 */ /* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */ /* UART1_TXD */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */ /* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */ @@ -234,6 +234,8 @@ static const struct pad_config early_gpio_table[] = { static const struct pad_config late_gpio_table[] = { /* UART0_RXD */ PAD_CFG_GPI(GPP_C8, NONE, PLTRST), /* FP_INT */ /* UART0_TXD */ PAD_CFG_GPO(GPP_C9, 1, DEEP), /* FP_RST_ODL */ +/* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* PCH_FPS_MCU_NRST_ODL */ +/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FPS_MCU_BOOT0 */ }; #endif -- cgit v1.2.3