From 1950ed9ee3baaf3ecfd3fb2583bfdce562395cb7 Mon Sep 17 00:00:00 2001
From: Matt Delco <delco@chromium.org>
Date: Wed, 15 Aug 2018 11:51:43 -0700
Subject: mb/google/eve: enable eist

Enable Enhanced Intel SpeedStep (EIST) on eve.

Change-Id: I49b18b817cda570f5c3c4d048c4e03329ac10b87
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/28102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
---
 src/mainboard/google/eve/devicetree.cb | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/mainboard/google/eve/devicetree.cb')

diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index 16bfc47a59..c1482c6296 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -7,6 +7,8 @@ chip soc/intel/skylake
 	register "deep_s5_enable_dc" = "1"
 	register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN"
 
+	register "eist_enable" = "1"
+
 	# GPE configuration
 	# Note that GPE events called out in ASL code rely on this
 	# route. i.e. If this route changes then the affected GPE
-- 
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