From 81485d2763f461ce28dad2ffc43441c4bae570dd Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Fri, 28 Oct 2016 09:13:52 -0700 Subject: google/eve: Add new board Add the eve board files using kabylake and FSP 2.0. BUG=chrome-os-partner:58666 TEST=build and boot on eve board Change-Id: I7ca71fe052608d710ee65d078df7af7b55d382bc Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/17177 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/eve/acpi/dptf.asl | 97 +++++++++++++++++++++++++++++++ src/mainboard/google/eve/acpi/ec.asl | 14 +++++ src/mainboard/google/eve/acpi/superio.asl | 14 +++++ 3 files changed, 125 insertions(+) create mode 100644 src/mainboard/google/eve/acpi/dptf.asl create mode 100644 src/mainboard/google/eve/acpi/ec.asl create mode 100644 src/mainboard/google/eve/acpi/superio.asl (limited to 'src/mainboard/google/eve/acpi') diff --git a/src/mainboard/google/eve/acpi/dptf.asl b/src/mainboard/google/eve/acpi/dptf.asl new file mode 100644 index 0000000000..95985f6a41 --- /dev/null +++ b/src/mainboard/google/eve/acpi/dptf.asl @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 99 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "Ambient" +#define DPTF_TSR0_PASSIVE 55 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "Charger" +#define DPTF_TSR1_PASSIVE 55 +#define DPTF_TSR1_CRITICAL 75 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "DRAM" +#define DPTF_TSR2_PASSIVE 50 +#define DPTF_TSR2_CRITICAL 75 + +#define DPTF_TSR3_SENSOR_ID 4 +#define DPTF_TSR3_SENSOR_NAME "eMMC" +#define DPTF_TSR3_PASSIVE 50 +#define DPTF_TSR3_CRITICAL 75 + +#undef DPTF_ENABLE_FAN_CONTROL +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0xbb8, "mA", 0 }, /* 3000mA (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x800, "mA", 0 }, /* 2000mA */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1000mA */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 500mA */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0mA */ +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, + + /* CPU Effect on Ambient */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on Charger */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on DRAM */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 90, 0, 0, 0, 0 }, + + /* CPU Effect on eMMC */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on Charger (TSR1) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on eMMC (TSR3) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR3, 200, 600, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 2500, /* PowerLimitMinimum */ + 4500, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 250 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 7000, /* PowerLimitMinimum */ + 7000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) + +/* Include DPTF */ +#include diff --git a/src/mainboard/google/eve/acpi/ec.asl b/src/mainboard/google/eve/acpi/ec.asl new file mode 100644 index 0000000000..778285107c --- /dev/null +++ b/src/mainboard/google/eve/acpi/ec.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ diff --git a/src/mainboard/google/eve/acpi/superio.asl b/src/mainboard/google/eve/acpi/superio.asl new file mode 100644 index 0000000000..778285107c --- /dev/null +++ b/src/mainboard/google/eve/acpi/superio.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ -- cgit v1.2.3