From 1ba34323010f075e21ed11d9cf2c97e688441676 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 2 Jun 2016 17:58:18 -0500 Subject: google/enguarde: Upstream Lenovo N21 Chromebook Migrate google/enguarde (Lenovo N21 Chromebook) from Chromium tree to upstream, using google/rambi as a reference. original source: branch firmware-enguarde-5216.201.B commit cf1f57b [Enguarde: Adjust rx delay for norm.] TEST=built and booted Linux on enguarde with full functionality blobs required for working image: VGA BIOS (vgabios.bin) firmware descriptor (ifd.bin) Intel ME firmware (me.bin) MRC (mrc.elf) external reference code (refcode.elf) Change-Id: I3ccda29d1e095d8b1b36766cda913172f72233a7 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/15444 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/google/enguarde/acpi/chromeos.asl | 32 +++ src/mainboard/google/enguarde/acpi/dptf.asl | 87 ++++++++ src/mainboard/google/enguarde/acpi/ec.asl | 20 ++ src/mainboard/google/enguarde/acpi/mainboard.asl | 266 +++++++++++++++++++++++ src/mainboard/google/enguarde/acpi/superio.asl | 27 +++ src/mainboard/google/enguarde/acpi/video.asl | 39 ++++ 6 files changed, 471 insertions(+) create mode 100644 src/mainboard/google/enguarde/acpi/chromeos.asl create mode 100644 src/mainboard/google/enguarde/acpi/dptf.asl create mode 100644 src/mainboard/google/enguarde/acpi/ec.asl create mode 100644 src/mainboard/google/enguarde/acpi/mainboard.asl create mode 100644 src/mainboard/google/enguarde/acpi/superio.asl create mode 100644 src/mainboard/google/enguarde/acpi/video.asl (limited to 'src/mainboard/google/enguarde/acpi') diff --git a/src/mainboard/google/enguarde/acpi/chromeos.asl b/src/mainboard/google/enguarde/acpi/chromeos.asl new file mode 100644 index 0000000000..50fc8d26fe --- /dev/null +++ b/src/mainboard/google/enguarde/acpi/chromeos.asl @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Fields are in the following order. + * - Type: recovery = 1 developer mode = 2 write protect = 3 + * - Active Level - if -1 not a valid gpio + * - GPIO number encoding - if -1 not a valid gpio + * - Chipset Name + * + * Note: On Bay Trail we need to encode gpios within the 3 separate banks + * with the MMIO offset of each banks space. e.g. GPIO_SUS[8] would be encoded + * as 0x2008 where the SUS offset (IO_BASE_OFFSET_GPSSUS) is 0x2000. + */ + +Name(OIPG, Package() { + // No physical recovery button + Package () { 0x0001, 0, 0xFFFFFFFF, "BayTrail" }, + Package () { 0x0003, 1, 0x2006, "BayTrail" }, +}) diff --git a/src/mainboard/google/enguarde/acpi/dptf.asl b/src/mainboard/google/enguarde/acpi/dptf.asl new file mode 100644 index 0000000000..cf82fa6e0f --- /dev/null +++ b/src/mainboard/google/enguarde/acpi/dptf.asl @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 70 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 }, /* 0.128A */ +}) + +/* Mainboard specific _PDL is 1GHz */ +Name (MPDL, 8) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, +#endif + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 2 */ + Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, // Revision + Package () { // Power Limit 1 + 0, // PowerLimitIndex, 0 for Power Limit 1 + 1600, // PowerLimitMinimum + 6200, // PowerLimitMaximum + 1000, // TimeWindowMinimum + 1000, // TimeWindowMaximum + 200 // StepSize + }, + Package () { // Power Limit 2 + 1, // PowerLimitIndex, 1 for Power Limit 2 + 8000, // PowerLimitMinimum + 8000, // PowerLimitMaximum + 1000, // TimeWindowMinimum + 1000, // TimeWindowMaximum + 1000 // StepSize + } +}) + +/* Include Baytrail DPTF */ +#include diff --git a/src/mainboard/google/enguarde/acpi/ec.asl b/src/mainboard/google/enguarde/acpi/ec.asl new file mode 100644 index 0000000000..fb81ae08ec --- /dev/null +++ b/src/mainboard/google/enguarde/acpi/ec.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* mainboard configuration */ +#include + +/* ACPI code for EC functions */ +#include diff --git a/src/mainboard/google/enguarde/acpi/mainboard.asl b/src/mainboard/google/enguarde/acpi/mainboard.asl new file mode 100644 index 0000000000..01868e4f4d --- /dev/null +++ b/src/mainboard/google/enguarde/acpi/mainboard.asl @@ -0,0 +1,266 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +Scope (\_SB) +{ + Device (LID0) + { + Name (_HID, EisaId ("PNP0C0D")) + Name (_PRW, Package() { BOARD_PCH_WAKE_GPIO, 0x5 }) + Method (_LID, 0) + { + Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS) + Return (\LIDS) + } + } + + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + Name (_UID, 1) + } + + /* Wake device for touchpad */ + Device (TPAD) + { + Name (_HID, EisaId ("PNP0C0E")) + Name (_UID, 1) + Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) + + Name (RBUF, ResourceTemplate() + { + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_TRACKPAD_IRQ + } + }) + + Method (_CRS) + { + /* Return interrupt if I2C1 is PCI mode */ + If (LEqual (\S1EN, 0)) { + Return (^RBUF) + } + + /* Return empty resource template otherwise */ + Return (ResourceTemplate() {}) + } + } +} + +Scope (\_SB.I2C1) +{ + Device (ATPB) + { + Name (_HID, "ATML0000") + Name (_DDN, "Atmel Touchpad Bootloader") + Name (_UID, 1) + Name (ISTP, 1) /* Touchpad */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x25, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.I2C1", // ResourceSource + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_TRACKPAD_IRQ + } + }) + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } + + Device (ATPA) + { + Name (_HID, "ATML0000") + Name (_DDN, "Atmel Touchpad") + Name (_UID, 2) + Name (ISTP, 1) /* Touchpad */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x4b, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.I2C1", // ResourceSource + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_TRACKPAD_IRQ + } + }) + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } + + Device (ETPA) + { + Name (_HID, "ELAN0000") + Name (_DDN, "Elan Touchpad") + Name (_UID, 3) + Name (ISTP, 1) /* Touchpad */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x15, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.I2C1", // ResourceSource + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_TRACKPAD_IRQ + } + }) + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } +} + +Scope (\_SB.I2C2) +{ + Device (CODC) + { + /* + * TODO(dlaurie): Need official HID. + * + * The current HID is created from the Maxim Integrated + * PCI Vendor ID 193Ch and a shortened device identifier. + */ + Name (_HID, "193C9890") + Name (_DDN, "Maxim 98090 Codec") + Name (_UID, 1) + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x10, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.I2C2", // ResourceSource + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_CODEC_IRQ + } + }) + + Method (_STA) + { + If (LEqual (\S2EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + } +} + +Scope (\_SB.I2C5) +{ + Device (ALSI) + { + /* + * TODO(dlaurie): Need official HID. + * + * The current HID is created from the Intersil PNP + * Vendor ID "LSD" and a shortened device identifier. + */ + Name (_HID, EisaId ("LSD2918")) + Name (_DDN, "Intersil 29018 Ambient Light Sensor") + Name (_UID, 1) + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x44, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.I2C5", // ResourceSource + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_ALS_IRQ + } + }) + + Method (_STA) + { + If (LEqual (\S5EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + } +} + +Scope (\_SB.LPEA) +{ + Name (GBUF, ResourceTemplate () + { + /* Jack Detect (index 0) */ + GpioInt (Edge, ActiveHigh, Exclusive, PullNone,, + "\\_SB.GPSC") { 14 } + + /* Mic Detect (index 1) */ + GpioInt (Edge, ActiveHigh, Exclusive, PullNone,, + "\\_SB.GPSC") { 15 } + }) +} diff --git a/src/mainboard/google/enguarde/acpi/superio.asl b/src/mainboard/google/enguarde/acpi/superio.asl new file mode 100644 index 0000000000..b8d7be0e51 --- /dev/null +++ b/src/mainboard/google/enguarde/acpi/superio.asl @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* mainboard configuration */ +#include +#include + +#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources +#define SIO_EC_HOST_ENABLE // EC Host Interface Resources +#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard +// Override default IRQ settings +#define SIO_EC_PS2K_IRQ Interrupt(ResourceConsumer, Edge, ActiveLow) {BOARD_I8042_IRQ} + +/* ACPI code for EC SuperIO functions */ +#include diff --git a/src/mainboard/google/enguarde/acpi/video.asl b/src/mainboard/google/enguarde/acpi/video.asl new file mode 100644 index 0000000000..1405b04031 --- /dev/null +++ b/src/mainboard/google/enguarde/acpi/video.asl @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Brightness write +Method (BRTW, 1, Serialized) +{ + // TODO +} + +// Hot Key Display Switch +Method (HKDS, 1, Serialized) +{ + // TODO +} + +// Lid Switch Display Switch +Method (LSDS, 1, Serialized) +{ + // TODO +} + +// Brightness Notification +Method(BRTN,1,Serialized) +{ + // TODO (no displays defined yet) +} + -- cgit v1.2.3