From edac4ef6d4c25414bc0e6200875d57fff9e3346e Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 9 Oct 2020 08:50:14 -0700 Subject: mb, soc/intel: Reorganize CNVi device entries in devicetree This change reorganizes the CNVi device entries in mainboard devicetree/overridetree and SoC chipset tree to make it consistent with how other SoC internal PCI devices are represented i.e. without a chip driver around the SoC controller itself. Before: chip drivers/wifi/generic register "wake" = "..." device pci xx.y on end end After: device pci xx.y on chip drivers/wifi/generic register "wake" = "..." device generic 0 on end end end Change-Id: I22660047a3afd5994400341de0ca461bbc0634e2 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/46865 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/mainboard/google/drallion/variants/drallion/devicetree.cb | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'src/mainboard/google/drallion') diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index de3b5ca8ea..aeacaa48dd 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -327,10 +327,12 @@ chip soc/intel/cannonlake end end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - chip drivers/wifi/generic - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "PME_B0_EN_BIT" + device generic 0 on end + end + end # CNVi wifi device pci 14.5 off end # SDCard device pci 15.0 on chip drivers/i2c/hid -- cgit v1.2.3