From 86f29118d37d0fa35ed5e20668336f852cd12550 Mon Sep 17 00:00:00 2001
From: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Date: Mon, 9 Sep 2019 14:05:33 -0700
Subject: mb/google/drallion: Enable 360 sensor detection

Implementing logic to detect SKU model and enable ISH accordignly.

BUG=b:140748790

Change-Id: I22fafb43dce6545851883be556a02d65a01fc386
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35303
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/drallion/Makefile.inc         |  3 +++
 src/mainboard/google/drallion/romstage.c           |  5 +++++
 .../baseboard/include/baseboard/variants.h         | 23 ++++++++++++++++++++++
 .../google/drallion/variants/drallion/gpio.c       | 16 +++++++++++++++
 .../variants/drallion/include/variant/gpio.h       |  3 +++
 5 files changed, 50 insertions(+)
 create mode 100644 src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h

(limited to 'src/mainboard/google/drallion')

diff --git a/src/mainboard/google/drallion/Makefile.inc b/src/mainboard/google/drallion/Makefile.inc
index e7c90bbcd2..ae8251e1d6 100644
--- a/src/mainboard/google/drallion/Makefile.inc
+++ b/src/mainboard/google/drallion/Makefile.inc
@@ -34,6 +34,9 @@ ramstage-y += ec.c
 romstage-y += ec.c
 verstage-y += ec.c
 
+subdirs-y += variants/baseboard
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
+
 subdirs-y += variants/$(VARIANT_DIR)
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
 
diff --git a/src/mainboard/google/drallion/romstage.c b/src/mainboard/google/drallion/romstage.c
index 20eee7f34b..c9f009e599 100644
--- a/src/mainboard/google/drallion/romstage.c
+++ b/src/mainboard/google/drallion/romstage.c
@@ -16,6 +16,9 @@
 #include <ec/google/wilco/romstage.h>
 #include <soc/cnl_memcfg_init.h>
 #include <soc/romstage.h>
+#include <baseboard/variants.h>
+
+void __weak variant_mainboard_post_init_params(FSPM_UPD *mupd) {}
 
 static const struct cnl_mb_cfg memcfg = {
 	/* Access memory info through SMBUS. */
@@ -57,6 +60,8 @@ static const struct cnl_mb_cfg memcfg = {
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
+	variant_mainboard_post_init_params(memupd);
+
 	wilco_ec_romstage_init();
 
 	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
diff --git a/src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h
new file mode 100644
index 0000000000..1edd660bbe
--- /dev/null
+++ b/src/mainboard/google/drallion/variants/baseboard/include/baseboard/variants.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef BASEBOARD_VARIANTS_H
+#define BASEBOARD_VARIANTS_H
+
+#include <fsp/api.h>
+
+void variant_mainboard_post_init_params(FSPM_UPD *mupd);
+
+#endif /* BASEBOARD_VARIANTS_H */
diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c
index 064f96c21e..5fba04b0b2 100644
--- a/src/mainboard/google/drallion/variants/drallion/gpio.c
+++ b/src/mainboard/google/drallion/variants/drallion/gpio.c
@@ -15,6 +15,9 @@
 
 #include <variant/gpio.h>
 #include <vendorcode/google/chromeos/chromeos.h>
+#include <gpio.h>
+#include <soc/romstage.h>
+#include <baseboard/variants.h>
 
 /* Pad configuration in ramstage */
 static const struct pad_config gpio_table[] = {
@@ -271,3 +274,16 @@ const struct cros_gpio *variant_cros_gpios(size_t *num)
 	*num = ARRAY_SIZE(cros_gpios);
 	return cros_gpios;
 }
+
+static int is_ish_device_enabled(void)
+{
+	gpio_input(SENSOR_DET_360);
+	return gpio_get(SENSOR_DET_360) == 0;
+}
+
+void variant_mainboard_post_init_params(FSPM_UPD *mupd)
+{
+	FSP_M_CONFIG *fsp_m_cfg = &mupd->FspmConfig;
+	if (fsp_m_cfg->PchIshEnable)
+		fsp_m_cfg->PchIshEnable = is_ish_device_enabled();
+}
diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h
index 20cfbb8279..251b40e0d0 100644
--- a/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h
+++ b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h
@@ -25,6 +25,9 @@
 /* Recovery mode */
 #define GPIO_REC_MODE		GPP_E8
 
+/* Sensor detection pin */
+#define SENSOR_DET_360		GPP_H5
+
 /* Memory configuration board straps */
 #define GPIO_MEM_CONFIG_0	GPP_F12
 #define GPIO_MEM_CONFIG_1	GPP_F13
-- 
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