From 3de90d134494203556a81c47a6640ae101674114 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Tue, 4 Aug 2020 16:47:10 +0200 Subject: soc/intel/cnl: Set Heci1Disable depending on devicetree config MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently HECI1 gets enabled by the option HeciEnabled, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement/disablement of the HECI1 device. All corresponding mainboards were checked if the devicetree matches the HeciEnabled setting, and adjusted where necessary. Change-Id: I03dd3577fbe3f68b0abc2d196d016a4d26d88ce5 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/44177 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner --- src/mainboard/google/drallion/variants/drallion/devicetree.cb | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src/mainboard/google/drallion/variants') diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index e9daf0d00d..4011693d34 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -30,7 +30,6 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "SaGv_Enabled" - register "HeciEnabled" = "0" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "PchPmSlpS3MinAssert" = "3" # 50ms @@ -418,7 +417,7 @@ chip soc/intel/cannonlake end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 + device pci 16.0 off end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection -- cgit v1.2.3