From 8cced29eed33285e0a086231c567f4633372f004 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 11 Sep 2019 10:32:31 +0530 Subject: =?UTF-8?q?soc/intel/cnl:=20Remove=20unnecessary=20FSP=20UPD=20?= =?UTF-8?q?=E2=80=9CPchPwrOptEnable=E2=80=9D=20usage?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PchPwrOptEnable FSP UPD is for internal testing and not really available in externally released FSP source hence assigning this UPD using devicetree config dmipwroptimize doesn't do anything. TEST=Build and boot sarien/arcada. Change-Id: I6da2a088fb697e57d12008fa18bd1764b3da7765 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/35323 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: V Sowmya --- src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb | 1 - 1 file changed, 1 deletion(-) (limited to 'src/mainboard/google/drallion/variants/sarien_cml') diff --git a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb index 84aacd58ec..f2367ffa1d 100644 --- a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb +++ b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb @@ -34,7 +34,6 @@ chip soc/intel/cannonlake register "speed_shift_enable" = "1" register "s0ix_enable" = "1" register "dptf_enable" = "1" - register "dmipwroptimize" = "1" register "satapwroptimize" = "1" register "AcousticNoiseMitigation" = "1" register "SlowSlewRateForIa" = "2" -- cgit v1.2.3