From d19b3ca90d50e8b1d11e153d913f0eceaf8552a0 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 1 Aug 2019 11:00:17 +0530 Subject: soc/intel/icelake: Make use of common thermal code for ICL This patch ports CB:34522 and CB:33147 changes from CNL to ICL. TEST=Build and boot dragonegg Change-Id: I0b983005f16fe182e634eac63fef4f6b22197a85 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/34649 Reviewed-by: Aamir Bohra Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb') diff --git a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb index b3b93f55ca..bcad954885 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb @@ -148,6 +148,7 @@ chip soc/intel/icelake #| | required to set up a BAR | #| | for TPM communication | #| | before memory is up | + #| pch_thermal_trip | PCH Trip Temperature | #+-------------------+---------------------------+ register "common_soc_config" = "{ @@ -165,6 +166,7 @@ chip soc/intel/icelake .sda_hold = 36, } }, + .pch_thermal_trip = 77, }" # GPIO PM programming @@ -181,7 +183,7 @@ chip soc/intel/icelake device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device device pci 04.0 off end # SA Thermal device - device pci 12.0 off end # Thermal Subsystem + device pci 12.0 on end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 device pci 14.0 on -- cgit v1.2.3