From 3a14338625d6ae7c6c4e8ee0b1e9be285593b3a6 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Wed, 11 Jul 2018 12:07:51 +0530 Subject: mb/google/dragonegg: Add initial mainboard code support This patch includes support for both ICL ES0 and ES1 samples. Detailed document is here: Documentation/soc/intel/icelake/iceLake_coreboot_development.md TEST=Able to build and boot dragonegg. Change-Id: I2cc269cb0050bf5b031f48cfe114485c55ab8fa9 Signed-off-by: Aamir Bohra Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/29749 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/google/dragonegg/chromeos.c | 56 +++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 src/mainboard/google/dragonegg/chromeos.c (limited to 'src/mainboard/google/dragonegg/chromeos.c') diff --git a/src/mainboard/google/dragonegg/chromeos.c b/src/mainboard/google/dragonegg/chromeos.c new file mode 100644 index 0000000000..fa388e5379 --- /dev/null +++ b/src/mainboard/google/dragonegg/chromeos.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#if ENV_RAMSTAGE +#include + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), + "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} +#endif /* ENV_RAMSTAGE */ + +int get_write_protect_state(void) +{ + /* Read PCH_WP GPIO. */ + return gpio_get(GPIO_PCH_WP); +} + +void mainboard_chromeos_acpi_generate(void) +{ + const struct cros_gpio *gpios; + size_t num; + + gpios = variant_cros_gpios(&num); + chromeos_acpi_gpio_generate(gpios, num); +} -- cgit v1.2.3