From 2255ebaa23d5741e9f6179bfe8b6b3850b143ce8 Mon Sep 17 00:00:00 2001 From: Varun Joshi Date: Tue, 31 Mar 2020 18:02:33 -0700 Subject: mb/google/deltaur: Add support to enable GbE on variant - Configure devicetree for enabling GbE on variant and remove from baseboard. - Configure Kconfig to enable GbE region. - Configure fmd to incorporate GbE. BUG=b:151102809 Cq-Depend: chrome-internal:2843183 Signed-off-by: Varun Joshi Change-Id: I1c36b132546049e3e775585c41164072f4ece73e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40001 Tested-by: build bot (Jenkins) Reviewed-by: EricR Lai Reviewed-by: Tim Wawrzynczak Reviewed-by: Bora Guvendik --- src/mainboard/google/deltaur/variants/baseboard/devicetree.cb | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'src/mainboard/google/deltaur/variants/baseboard/devicetree.cb') diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index a63d66c834..a30c12d633 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -59,11 +59,6 @@ chip soc/intel/tigerlake register "PcieClkSrcUsage[4]" = "6" register "PcieClkSrcClkReq[4]" = "4" - # PCIe port root 8 (LAN), clock 3 - register "PcieRpEnable[7]" = "1" - register "PcieClkSrcUsage[3]" = "PCIE_CLK_LAN" - register "PcieClkSrcClkReq[3]" = "3" - # PCIe root port 9 (NVMe), clock 2 register "PcieRpEnable[8]" = "1" register "PcieClkSrcUsage[2]" = "8" @@ -332,7 +327,7 @@ chip soc/intel/tigerlake device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI Flash Controller - device pci 1f.6 on end # GbE Controller + device pci 1f.6 off end # GbE Controller device pci 1f.7 off end # Intel Trace Hub end end -- cgit v1.2.3