From 06684979f9ebfa2731bc01a5b9cfb61a4e91a2c0 Mon Sep 17 00:00:00 2001
From: Varun Joshi <varun.joshi@intel.corp-partner.google.com>
Date: Tue, 17 Mar 2020 22:52:56 -0700
Subject: mb/google/deltaur: Update onboard memory config

Update dq, dqs map based on deltan schematics.
Configure memory to read SPD.

BUG=b:151702387

Signed-off-by: Varun Joshi <varun.joshi@intel.corp-partner.google.com>
Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
---
 src/mainboard/google/deltaur/romstage.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
 create mode 100644 src/mainboard/google/deltaur/romstage.c

(limited to 'src/mainboard/google/deltaur/romstage.c')

diff --git a/src/mainboard/google/deltaur/romstage.c b/src/mainboard/google/deltaur/romstage.c
new file mode 100644
index 0000000000..2d7362976f
--- /dev/null
+++ b/src/mainboard/google/deltaur/romstage.c
@@ -0,0 +1,14 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <baseboard/variants.h>
+#include <soc/romstage.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
+	variant_memory_init(mem_cfg);
+}
-- 
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