From 5aa511931f5a1069be1803f4f8fb4182e8d779ab Mon Sep 17 00:00:00 2001 From: Tao Xia Date: Mon, 5 Jul 2021 14:23:01 +0800 Subject: mb/google/dedede/var/storo: Update DPTF parameters Update DPTF parameters from internal thermal team. BUG=b:180875582 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Tao Xia Change-Id: I6d87bc63a66ff38bc2f706d58b8537c052bf4594 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56069 Tested-by: build bot (Jenkins) Reviewed-by: Weimin Wu Reviewed-by: Karthik Ramasubramanian --- src/mainboard/google/dedede/variants/storo/overridetree.cb | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/mainboard/google/dedede') diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb index 7ddadbded8..e8246522b9 100644 --- a/src/mainboard/google/dedede/variants/storo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb @@ -77,16 +77,16 @@ chip soc/intel/jasperlake .tdp_pl2_override = 20, }" - register "tcc_offset" = "5" # TCC of 100C + register "tcc_offset" = "10" # TCC of 95C device domain 0 on device pci 04.0 on chip drivers/intel/dptf ## Passive Policy register "policies.passive" = "{ - [0] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 60, 3000), - [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 60, 3000), - [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 60, 3000),}" + [0] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 67, 3000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 67, 3000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 67, 3000),}" ## Critical Policy register "policies.critical" = "{ [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), -- cgit v1.2.3