From 3eed673659f62321a48d4d3f1b2a7005eb272493 Mon Sep 17 00:00:00 2001 From: Daniel_Peng Date: Tue, 22 Aug 2023 10:07:54 +0800 Subject: mb/google/dedede/var/pirika: Add USB2 PHY parameters for Type-A/Type-C This change are added fine-tuned USB2 PHY parameters to improve the USB2 eye diagram result. BUG=b:296493887 BRANCH=firmware-dedede-13606.B TEST=Local build bios successfully. And verified the USB2 eye diagram test result. Change-Id: I915fe689883267901e8faba28632345d8c227c28 Signed-off-by: Daniel_Peng Reviewed-on: https://review.coreboot.org/c/coreboot/+/77359 Reviewed-by: Eric Lai Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/mainboard/google/dedede/variants/pirika/overridetree.cb | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'src/mainboard/google/dedede') diff --git a/src/mainboard/google/dedede/variants/pirika/overridetree.cb b/src/mainboard/google/dedede/variants/pirika/overridetree.cb index 11d82a254c..1c4abaa6d5 100644 --- a/src/mainboard/google/dedede/variants/pirika/overridetree.cb +++ b/src/mainboard/google/dedede/variants/pirika/overridetree.cb @@ -51,12 +51,22 @@ chip soc/intel/jasperlake }" # USB Port Configuration + register "usb2_ports[0]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-C Port C0 register "usb2_ports[2]" = "{ .enable = 1, .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, .pre_emp_bias = USB2_BIAS_28P15MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A + }" # Type-A Port A0 register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera register "usb2_ports[7]" = "{ .enable = 1, -- cgit v1.2.3