From 7a04d05f1d54f93ae8d4d7b53eb5c1119446da49 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Wed, 9 Sep 2020 14:34:36 +0530 Subject: mb/google/dedede: Enable SaGv support Allow MRC training in SaGv low, mid and high frequencies. TEST=Verify memory trains at low, mid and high SaGv point through FSP debug logs enabled. Change-Id: I0f60aad031ce9dfe23e54426753311c35db46c05 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/45196 Reviewed-by: Angel Pons Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mainboard/google/dedede/variants') diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index fe232e68d3..b2ed21afc3 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -168,6 +168,9 @@ chip soc/intel/jasperlake # Skip the CPU repalcement check register "SkipCpuReplacementCheck" = "1" + # Sagv Configuration + register "SaGv" = "SaGv_Enabled" + # Set the minimum assertion width register "PchPmSlpS3MinAssert" = "3" # 50ms register "PchPmSlpS4MinAssert" = "1" # 1s -- cgit v1.2.3