From 5a702653cdc9562ece3c7ab5da121d42af7edb10 Mon Sep 17 00:00:00 2001 From: Stanley Wu Date: Mon, 8 Mar 2021 23:09:12 +0800 Subject: mb/google/dedede/var/boten: Adjust p-sensor detect distance to 20mm MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit P-sensor vendor fine-tune detect distance as 20mm for WWAN SAR table switch. BUG=b:179000150 BRANCH=dedede TEST=run "i2cdump -y -f 15 0x28" to confirm registers as expected. un-approach： => register address: 0x01 value: 0x00 approach: => register address: 0x01 value: 0x02 Confirm WWAN SAR table work as expected. Signed-off-by: Stanley Wu Change-Id: I659721e60aa0766ed4c277dae43ded222e18ad1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51343 Reviewed-by: Karthik Ramasubramanian Reviewed-by: Paul Fagerburg Tested-by: build bot (Jenkins) --- src/mainboard/google/dedede/variants/boten/overridetree.cb | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'src/mainboard/google/dedede/variants') diff --git a/src/mainboard/google/dedede/variants/boten/overridetree.cb b/src/mainboard/google/dedede/variants/boten/overridetree.cb index 6c0fdd62d1..9ff12bece4 100644 --- a/src/mainboard/google/dedede/variants/boten/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boten/overridetree.cb @@ -216,14 +216,14 @@ chip soc/intel/jasperlake register "reg_gnrl_ctrl0" = "0x0a" register "reg_gnrl_ctrl1" = "0x22" register "reg_afe_ctrl0" = "0x20" - register "reg_afe_ctrl3" = "0x00" + register "reg_afe_ctrl3" = "0x01" register "reg_afe_ctrl4" = "0x47" register "reg_afe_ctrl6" = "0x00" register "reg_afe_ctrl7" = "0x47" register "reg_afe_ctrl8" = "0x12" - register "reg_afe_ctrl9" = "0x08" + register "reg_afe_ctrl9" = "0x0f" register "reg_afe_ph0" = "0x37" - register "reg_afe_ph1" = "0x10" + register "reg_afe_ph1" = "0x29" register "reg_afe_ph2" = "0x1f" register "reg_afe_ph3" = "0x3d" register "reg_prox_ctrl0" = "0x0b" @@ -232,7 +232,7 @@ chip soc/intel/jasperlake register "reg_prox_ctrl3" = "0x20" register "reg_prox_ctrl4" = "0x0c" register "reg_prox_ctrl5" = "0x00" - register "reg_prox_ctrl6" = "0x1c" + register "reg_prox_ctrl6" = "0x2d" register "reg_prox_ctrl7" = "0xc0" register "reg_adv_ctrl0" = "0x00" register "reg_adv_ctrl1" = "0x00" @@ -252,13 +252,13 @@ chip soc/intel/jasperlake register "reg_adv_ctrl15" = "0x0c" register "reg_adv_ctrl16" = "0x04" register "reg_adv_ctrl17" = "0x70" - register "reg_adv_ctrl18" = "0x20" + register "reg_adv_ctrl18" = "0x40" register "reg_adv_ctrl19" = "0x00" register "reg_adv_ctrl20" = "0x00" register "reg_irq_msk" = "0x6f" register "reg_irq_cfg0" = "0x00" register "reg_irq_cfg1" = "0x80" - register "reg_irq_cfg2" = "0x01" + register "reg_irq_cfg2" = "0x00" device i2c 28 on end end end # I2C 5 -- cgit v1.2.3