From 30b854dccd1fce2d439fb70ffa15064130cad73c Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Tue, 29 Sep 2020 22:06:26 -0600 Subject: mb/google/dedede: Override GPIO PM configuration If Cr50 is running old firmware version and hence does not ensure long interrupt pulses, override the GPIO PM configuration. BUG=None TEST=Build and boot waddledee to OS. Ensure that any chip override happens before FSP silicon parameter initialization. Ensure that the suspend/resume sequence works fine. Ensure that the reboot sequence works fine for 50 iterations. Change-Id: I455c51d4a63b1b5edadbf00c786ce61b0ba1ff00 Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/45857 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Tim Wawrzynczak Reviewed-by: Nico Huber --- src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 8 -------- 1 file changed, 8 deletions(-) (limited to 'src/mainboard/google/dedede/variants') diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 73b0c61f1b..fe232e68d3 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -129,14 +129,6 @@ chip soc/intel/jasperlake # Select eDP for port A register "DdiPortAConfig" = "1" - # Disable PM to allow for shorter irq pulses - register "gpio_override_pm" = "1" - register "gpio_pm[0]" = "0" - register "gpio_pm[1]" = "0" - register "gpio_pm[2]" = "0" - register "gpio_pm[3]" = "0" - register "gpio_pm[4]" = "0" - # Enable HPD for DDI ports B/C register "DdiPortBHpd" = "1" register "DdiPortCHpd" = "1" -- cgit v1.2.3