From 2302fcf03962c03a6cf80c9978ba8e57ded0e3f6 Mon Sep 17 00:00:00 2001 From: FrankChu Date: Fri, 14 Jan 2022 11:36:35 +0800 Subject: mb/google/dedede/var/galtic: Decrease core display clock to 172.8 MHz Galtic has a rare stability issue. The symptom is display black screen while switching to secure mode, normally it will occurred at the last step of factory side and it'll follow by some specific SOCs. Slowing the initial core display clock frequency down to 172.8 MHz as per Intel recommend for short term solution for Gal series. The CdClock=0xff is set in dedede baseboard, and we overwrite it as 0x0 (172.8 MHz) for Galtic. BUG=b:206557434 BRANCH=dedede TEST=Build firmware and verify on fail DUTs. Check the DUTs can boot up in secure mode well. Signed-off-by: Frank Chu Change-Id: Ic059ab306f80a6d01f4b0a380a3b767d3245478d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61103 Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/mainboard/google/dedede/variants/galtic/overridetree.cb | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mainboard/google/dedede/variants') diff --git a/src/mainboard/google/dedede/variants/galtic/overridetree.cb b/src/mainboard/google/dedede/variants/galtic/overridetree.cb index 150bfe3331..8004736d31 100644 --- a/src/mainboard/google/dedede/variants/galtic/overridetree.cb +++ b/src/mainboard/google/dedede/variants/galtic/overridetree.cb @@ -67,6 +67,9 @@ chip soc/intel/jasperlake register "tcc_offset" = "8" # TCC of 97C + # Core Display Clock Frequency selection + register "cd_clock" = "CD_CLOCK_172_8_MHZ" + device domain 0 on device pci 04.0 on # Default DPTF Policy for all Dedede boards if not overridden -- cgit v1.2.3