From f354c8c6258aa30c545c78c454c2e174b19abeae Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Fri, 28 Feb 2020 17:00:14 -0700 Subject: mb/google/dedede: Configure WLAN Turn on CNVi device. Turn on PCIe Root port that hosts WLAN device. Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used for WLAN - both CNVi and M.2. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian Change-Id: I9bb8e57cdb688bc544929c94af380b9ef1d936a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39115 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/dedede/variants/waddledoo/overridetree.cb | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src/mainboard/google/dedede/variants/waddledoo') diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb index 061a0f865f..9860e3de46 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb @@ -49,5 +49,12 @@ chip soc/intel/tigerlake device i2c 15 on end end end #I2C 0 + + device pci 1c.7 on + chip drivers/intel/wifi + register "wake" = "GPE0_DW2_03" + device pci 00.0 on end + end + end # PCI Express Root Port 8 - WLAN end end -- cgit v1.2.3