From 3d80d14cd4ed82e74057cea884dcb9bb7588c076 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Fri, 12 Jan 2024 16:22:19 +0100 Subject: soc/intel/jasperlake: Drop redundant PcieRpEnable The PcieRpEnable option is redundant to our on/off setting in the devicetrees. Let's use the common coreboot infrastructure instead. Thanks to Nicholas for doing all the mainboard legwork! Change-Id: Iea7f616f6db579c06722369c08de7cf7261dece8 Signed-off-by: Nico Huber Signed-off-by: Nicholas Sudsgaard Reviewed-on: https://review.coreboot.org/c/coreboot/+/79919 Reviewed-by: Matt DeVillier Reviewed-by: Paul Menzel Reviewed-by: Jonathon Hall Tested-by: build bot (Jenkins) --- src/mainboard/google/dedede/variants/sasukette/overridetree.cb | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src/mainboard/google/dedede/variants/sasukette/overridetree.cb') diff --git a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb index 5e4de2ac2a..1b1df26db1 100644 --- a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb +++ b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb @@ -8,8 +8,6 @@ fw_config end chip soc/intel/jasperlake - # Disable PCIe Root Port 8 (index 7) - register "PcieRpEnable[7]" = "0" # Disable PCIe Clock Source 4 (index 3) register "PcieClkSrcUsage[3]" = "0xff" @@ -227,6 +225,7 @@ chip soc/intel/jasperlake end end end #I2C 4 + device pci 1c.7 off end # PCI Express Root Port 8 device pci 1f.3 on chip drivers/generic/alc1015 register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)" -- cgit v1.2.3