From 0af1926353d48242f03d6c80c6b2c8f646a3c145 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sun, 4 Oct 2020 12:13:07 -0700 Subject: drivers/wifi: Drop maxsleep parameter from chip config MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This change drops maxsleep parameter from chip config and instead hardcodes the deepest sleep state from which the WiFi device can wake the system up from to SLP_TYP_S3. This is similar to how other device drivers in coreboot report _PRW property in ACPI. It relieves the users from adding another register attribute to devicetree since all mainboards configure the same value. If this changes in the future, it should be easy to bring the maxsleep config parameter back. BUG=b:169802515 BRANCH=zork Change-Id: I42131fced008da0d51f0f777b7f2d99deaf68827 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/46033 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/dedede/variants/magolor/overridetree.cb | 1 - 1 file changed, 1 deletion(-) (limited to 'src/mainboard/google/dedede/variants/magolor') diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb index 8a83b83028..f41e9fab6b 100644 --- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb +++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb @@ -287,7 +287,6 @@ chip soc/intel/jasperlake device pci 1c.7 on chip drivers/wifi/generic register "wake" = "GPE0_DW2_03" - register "maxsleep" = "3" device pci 00.0 on end end end # PCI Express Root Port 8 - WLAN -- cgit v1.2.3