From cf1996def838afbe2a650ec68bdcf6f9addc81cd Mon Sep 17 00:00:00 2001
From: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Date: Mon, 9 Aug 2021 11:26:59 +0800
Subject: mb/google/dedede/var/cret: Fix DPTF passive and critical policies

TSR2 thermal sensor doesn't define in cret. Fix DPTF passive and
critical policies for getting negative temperatures in OS.

BUG=b:195868075
BRANCH=dedede
TEST=Build and boot to OS in cret. Ensure that the DPTF entries look
correct in both static.c and SSDT tables i.e. passive and critical
policies for applicable devices only are present.

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I849662cbb3adc8e528d65af2c90e7c8e4880d607
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
---
 .../google/dedede/variants/cret/overridetree.cb    | 36 ++++++++++++++++++++++
 1 file changed, 36 insertions(+)

(limited to 'src/mainboard/google/dedede/variants/cret/overridetree.cb')

diff --git a/src/mainboard/google/dedede/variants/cret/overridetree.cb b/src/mainboard/google/dedede/variants/cret/overridetree.cb
index be84c79fde..afed775122 100644
--- a/src/mainboard/google/dedede/variants/cret/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/cret/overridetree.cb
@@ -57,6 +57,42 @@ chip soc/intel/jasperlake
 		},
 	}"
 	device domain 0 on
+		device pci 04.0 on
+			chip drivers/intel/dptf
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU, CPU,           90, 10000),
+					[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000),
+					[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 15000)
+				}"
+
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,           105, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN)
+				}"
+
+				## Power Limits Control
+				register "controls.power_limits" = "{
+					.pl1 = {
+						.min_power = 3000,
+						.max_power = 6000,
+						.time_window_min = 1 * MSECS_PER_SEC,
+						.time_window_max = 1 * MSECS_PER_SEC,
+						.granularity = 200,
+					},
+					.pl2 = {
+						.min_power = 20000,
+						.max_power = 20000,
+						.time_window_min = 1 * MSECS_PER_SEC,
+						.time_window_max = 1 * MSECS_PER_SEC,
+						.granularity = 1000,
+					}
+				}"
+				device generic 0 on end
+			end
+		end # SA Thermal device
 		device pci 14.0 on
 			chip drivers/usb/acpi
 				device usb 0.0 on
-- 
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