From 501e3c1837ba527ba8e49753688ca73af022df51 Mon Sep 17 00:00:00 2001
From: Karthikeyan Ramasubramanian <kramasub@google.com>
Date: Tue, 7 Jan 2020 16:21:10 -0700
Subject: mb/google/dedede: Enable EC

Perform EC initialization in bootblock and ramstages. Add associated ACPI
configuration.

BUG=b:144768001
TEST=Build Test.

Change-Id: Ib31ae190818c8870bdd46ea6c3d9ca70dc0485cc
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
---
 src/mainboard/google/dedede/dsdt.asl | 9 +++++++++
 1 file changed, 9 insertions(+)

(limited to 'src/mainboard/google/dedede/dsdt.asl')

diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl
index 3e278e3e9d..3d17017101 100644
--- a/src/mainboard/google/dedede/dsdt.asl
+++ b/src/mainboard/google/dedede/dsdt.asl
@@ -7,6 +7,7 @@
  */
 
 #include <arch/acpi.h>
+#include <variant/ec.h>
 #include <variant/gpio.h>
 
 DefinitionBlock(
@@ -41,4 +42,12 @@ DefinitionBlock(
 	/* Chipset specific sleep states */
 	#include <southbridge/intel/common/acpi/sleepstates.asl>
 
+	/* Chrome OS Embedded Controller */
+	Scope (\_SB.PCI0.LPCB)
+	{
+		/* ACPI code for EC SuperIO functions */
+		#include <ec/google/chromeec/acpi/superio.asl>
+		/* ACPI code for EC functions */
+		#include <ec/google/chromeec/acpi/ec.asl>
+        }
 }
-- 
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